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PDF NUS5530MN Data sheet ( Hoja de datos )
| Número de pieza | NUS5530MN | |
| Descripción | Integrated Power MOSFET | |
| Fabricantes | ON Semiconductor | |
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NUS5530MN
Integrated Power MOSFET
with PNP Low VCE(sat)
Switching Transistor
This integrated device represents a new level of safety and
board−space reduction by combining the 20 V P−Channel FET with a
PNP Silicon Low VCE(sat) switching transistor. This newly integrated
product provides higher efficiency and accuracy for battery powered
portable electronics.
Features
• Low RDS(on) (MOSFET) and Low VCE(sat) (Transistor)
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive (MOSFET)
• Performance DFN Package
• This is a Pb−Free Device
Applications
• Power Management in Portable and Battery−Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS FOR P−CHANNEL FET
(TA = 25°C unless otherwise noted)
Rating
Symbol 5 sec
Steady
State
Unit
Drain−Source Voltage
Gate−Source Voltage
Continuous Drain Current
(TJ = 150°C) (Note 1)
TA = 25°C
TA = 85°C
Pulsed Drain Current
Continuous Source Current
(Note 1)
VDS −20 V
VGS "12 V
ID A
−5.3 −3.9
−3.8 −2.8
IDM "20 A
IS
−5.3 −3.9
A
Maximum Power Dissipation
(Note 1)
TA = 25°C
TA = 85°C
Operating Junction and Storage
Temperature Range
PD
TJ, Tstg
2.5 1.3
1.3 0.7
−55 to +150
W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size
(Cu area = 1.27 in sq [1 oz] including traces).
http://onsemi.com
18
27
36
45
(Top View)
8
1
DFN8
CASE 506AL
MARKING DIAGRAM
1 5530
AYWW G
G
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
Emitter 8
Base 7
N/C 6
Gate 5
Collector
Drain
1 N/C
2 Collector
3 Source
4 Drain
(Bottom View)
ORDERING INFORMATION
Device
Package
Shipping†
NUS5530MNR2G DFN8 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 0
1
Publication Order Number:
NUS5530MN/D
1 page  
NUS5530MN
TYPICAL ELECTRICAL CHARACTERISTICS FOR P−CHANNEL FET
20
−5 V
16
−4.5 V
−4 V
12
−3.5 V
−3 V
TJ = 25°C
−2.5 V
20
16
12
TJ = −55°C
25°C
125°C
8
−2 V
4
0 VGS = −1.5 V
0 0.5 1 1.5 2 2.5 3
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
0.2
0.15
ID = −3.9 A
TJ = 25°C
0.1
0.05
0
01 2 3 4
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
5
Figure 3. On−Resistance versus
Gate−to−Source Voltage
1.6
ID = −3.9 A
VGS = −4.5 V
1.4
8
4
0
0 0.5 1 1.5 2 2.5 3
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.2
0.15
TJ = 25°C
VGS = 2.5 V
0.1
0.05
VGS = 3.6 V
VGS = 4.5 V
0
2 6 10 14 18 20
−ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.2
1
0.8
0.6
−50
−25 0
25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
150
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5
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| PDF Descargar | [ Datasheet NUS5530MN.PDF ] | |
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