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PDF CDB4265 Data sheet ( Hoja de datos )
| Número de pieza | CDB4265 | |
| Descripción | Evaluation Board | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CDB4265
Evaluation Board for CS4265
Features
z Single-ended Analog Inputs
z Single-ended Analog Outputs
z Coaxial and Optical Connections for CS4265
S/PDIF Transmitter Output
z CS8416 S/PDIF Digital Audio Receiver
z Header for Optional External Software
Configuration of CS4265
z Header for External PCM Serial Audio I/O
z 3.3 V Logic Interface
z Pre-defined Software Scripts
z Demonstrates Recommended Layout and
Grounding Arrangements
z Windows® Compatible Software Interface
to Configure CS4265 and Inter-board
Connections
ORDERING INFORMATION
CDB4265
Evaluation Board
Description
The CDB4265 evaluation board is an excellent means
for evaluating the CS4265 CODEC. Evaluation requires
an analog/digital signal source and analyzer, and power
supplies. A Windows® PC compatible computer must be
used to evaluate the CS4265.
System timing for the I²S, Left-Justified and Right-Justi-
fied interface formats can be provided by the CS4265,
the CS8416, or by a PCM I/O stake header with an ex-
ternal source connected.
RCA phono jacks are provided for the CS4265 analog in-
puts and outputs. Digital data I/O is available via RCA
phono or optical connectors to the CS8416 and CS4265.
The Windows® software provides a GUI to make config-
uration of the CDB4265 easy. The software
communicates through the PC’s serial port to configure
the control port registers so that all features of the
CS4265 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
I
Passive Input Filter
Active Input Filter
Microphone Input
M
U
X
CS4265
Control Port Interface
FPGA
Sub-clocks and Data
Passive Output Filter
Active Output Filter
S/PDIF Output Circuits
Test Points
Master Clock
Canned
Oscillator
CS8416
Header
Cirrus Logic, Inc.
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
FEB ‘05
DS657DB1
1 page  
CDB4265
1.7 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the headers J15, and
J17.
The 14-pin, 2 row header, J15, provides access to the serial audio signals required to interface to the serial
audio port of the CS4265 with a DSP (see Figure 11).
The direction of the signals on header J15 can be configured using the controls located within the Board
Controls group box on the CDB4265 Controls tab in the provided GUI software.
The 12-pin, 3 row header, J17, allows the user bidirectional access to the SPI/I2C control signals by simply
removing all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable
to the “EXT CONTROL” position. A single “GND” row for the ribbon cable’s ground connection is provided
to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user choose to
use the CDB for the I2C power rail.
1.8 Analog Inputs
RCA connectors supply the CS4265 analog inputs through single-ended, unity gain, active or passive cir-
cuits. Refer to the CS4265 data sheet for the ADC full-scale level.
A 4-pin CD-ROM type header is provided for easily connecting the analog outputs from a CD-ROM drive to
the analog inputs of the CS4265.
1.9 Analog Outputs
The CS4265 analog outputs are routed through a two-pole active filter. The output of the filter is connected
to RCA jacks for easy evaluation.
1.10
Serial Control Port
A graphical user interface is included with the CDB4265 to allow easy manipulation of the registers in the
CS4265, CS8416, and FPGA. See the device-specific data sheets for the CS4265, CS8416, and CD8406
internal register descriptions. The internal register map for the FPGA is located in section 4 on page 11.
Connecting a cable to the RS-232 connector (J19) and launching the Cirrus Logic FlexGUI software (Flex-
Loader.exe) will enable the CDB4265.
Refer to “PC Software Control” on page 7 for a description of the Graphical User Interface (GUI).
1.11 USB Control Port
The USB control port connector (J29) is currently unavailable.
DS657DB1
5
5 Page 
CDB4265
4. FPGA REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function
01h Code Rev. ID
7
Rev7
6
Rev6
5
Rev5
4
Rev4
3
Rev3
2
Rev2
02h MCLK Source
03h Subclock
Source
03h CS4265 SDIN
Source
04h Transmitter
SDIN Source
xx
Reserved Reserved
00
x
MCLK1
1
x
MCLK0
0
x
Reserved
0
x
Reserved
0
Reserved Reserved Reserved Reserved Reserved Reserved
00
0
1
0
0
Reserved SDIN2.2 SDIN2.1 SDIN2.0 Reserved SDIN1.2
00
0
0
0
0
Reserved Reserved Reserved Reserved Reserved TXSDIN2
00
0
1
0
0
1
Rev1
x
Reserved
0
SUBCLK1
0
SDIN1.1
0
TXSDIN1
0
0
Rev0
x
Reserved
0
SUBCLK0
1
SDIN1.0
0
TXSDIN0
1
DS657DB1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CDB4265.PDF ] | |
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