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CDB5364 PDF даташит

Спецификация CDB5364 изготовлена ​​​​«Cirrus Logic» и имеет функцию, называемую «Evaluation Board».

Детали детали

Номер произв CDB5364
Описание Evaluation Board
Производители Cirrus Logic
логотип Cirrus Logic логотип 

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CDB5364 Даташит, Описание, Даташиты
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CDB5364
Evaluation Board for CS5364
Features
! Single-Ended to Differential Analog Inputs
! 3.3 V Logic Interface
! Connection for DSP Serial I/O
! Windows®-Compatible CDB5364 Software
Supplied by Cirrus to Configure the CS5364
! On-Board CS8406 to Generate S/PDIF and
EIAJ-340 Digital Audio
Description
The CDB5364 evaluation board is an excellent means
for quickly evaluating the CS5364 24-bit, 192 kHz A/D
converter. Evaluation requires only a digital signal ana-
lyzer, an analog signal source, and a power supply.
On-board DIP switches configure the CS5364 in Stand-
Alone mode, avoiding the need for a PC.
For software-based device configuration, the Control
Port mode is used by attaching a host PC to the Evalu-
ation Board and executing the provided FlexGUI
software.
! Requires Only an Analog Signal Source, Power
Supplies and, optionally, a PC for a Complete
Analog-to-Digital-Converter Evaluation System
ORDERING INFORMATION
CDB5364
Evaluation Board
RS232
USB
8051 Micro
Control
I²C or SPI
RCA 4
Jacks
Analog
Input
Buffers
4
4
CS5364 A/D
Ain+
Ain-
Clks/Data
FPGA
S/PDIF
Output
CS8406
AES/EBU
S/PDIF
Transmitter
Optical
Coaxial
Buffers
http://www.cirrus.com
Audio
Clks/Data
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
SEPTEMBER '05
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CDB5364 Даташит, Описание, Даташиты
CDB5364
TABLE OF CONTENTS
1. CDB5364 System Overview..................................................................................................................... 3
2. Quick-Start Guide..................................................................................................................................... 3
3. Detailed Board Features .......................................................................................................................... 3
3.1 Stand-Alone Evaluation ............................................................................................................ 3
3.1.1 S1 and S4 Switch Operation .......................................................................................... 4
3.2 Control-Port Evaluation ............................................................................................................ 5
3.3 FlexGUI Hi-Level View ............................................................................................................. 6
3.4 FlexGUI Low-Level View .......................................................................................................... 7
3.5 Bit Definitions ........................................................................................................................... 8
3.5.1 CS5364 Bits .................................................................................................................... 8
3.5.2 FPGA Bits ....................................................................................................................... 8
4. CDB5364 Hardware ................................................................................................................................. 9
4.1 Input and Output Connectors ................................................................................................... 9
4.2 Switches ................................................................................................................................. 10
4.3 User Configuration Jumpers .................................................................................................. 10
4.4 Reserved Factory Programming Jumpers ............................................................................. 10
4.5 Power Supply Circuitry ........................................................................................................... 11
4.6 Grounding and Power Supply Treatment ............................................................................... 11
4.7 FPGA Hardware ..................................................................................................................... 11
4.8 CS8406 S/PDIF Audio Transmitter ........................................................................................ 11
4.9 Serial Audio Interface ............................................................................................................. 11
4.10 Analog Input Buffer .............................................................................................................. 11
5. Schematics............................................................................................................................................. 12
6. Board Layout and Routing Plots ........................................................................................................... 21
7. Revision History ..................................................................................................................................... 24
LIST OF FIGURES
Figure 1. Hi-Level FlexGUI View ................................................................................................................. 6
Figure 2. FlexGUI Low-Level Register View ............................................................................................... 7
Figure 3. FPGA Low-Level Bit View ............................................................................................................ 8
Figure 4. CS5364 (Schematic page 1) ...................................................................................................... 12
Figure 5. Clock Generation (Schematic page 2) ....................................................................................... 13
Figure 6. FPGA (Schematic page 3) ......................................................................................................... 14
Figure 7. Control Port (Schematic page 4) ................................................................................................ 15
Figure 8. Clock and Data Buffers (Schematic page 5) .............................................................................. 16
Figure 9. CD8406 S/PDIF Output (Schematic page 6) ............................................................................. 17
Figure 10. Analog Inputs 1 to 4 (Schematic page 7) ................................................................................. 18
Figure 11. Analog Inputs 5 to 8 (Schematic page 8) ................................................................................. 19
Figure 12. Power (Schematic page 9) ....................................................................................................... 20
Figure 13. Top Silkscreen ......................................................................................................................... 21
Figure 14. Top Layer ................................................................................................................................. 22
Figure 15. Bottom Layer ............................................................................................................................ 23
LIST OF TABLES
Table 1. CDB5364 Input and Output Connectors ....................................................................................... 9
Table 2. CDB5364 Switches ..................................................................................................................... 10
Table 3. User Jumpers .............................................................................................................................. 10
Table 4. CDB5364 Reserved Jumpers ..................................................................................................... 10
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CDB5364 Даташит, Описание, Даташиты
CDB5364
1. CDB5364 SYSTEM OVERVIEW
The CDB5364 Evaluation Board provides an excellent means of quickly evaluating the CS5364. A digital audio in-
terface transmitter (CS8406) provides an easy interface to digital audio signal analyzers, including the majority of
digital audio test equipment. Standard analog input and digital output connectors are included for quick and reliable
board setup. An on-board FPGA is used for configuring the various modes of the CS5364. Graphical User Interface
software is supplied by Cirrus Logic, which allows programming the CDB5364 when connected to a host PC running
Microsoft Windows®.
2. QUICK-START GUIDE
• Confirm that DIP switches S1 and S4 are in the closed (LO) position, pushed down to the right.
• Connect the following jumpers.
– J7 - Install 5 jumpers to the left side of J7, enabling the DIP switches to operate correctly.
– J81, J95 - Install jumpers to these positions, grounding XTI and XTO of the CS5364.
– J1 - Install a jumper at the +5 V position, allowing VA to be supplied by the +5 V supply.
• Install a 12.288 MHz canned Oscillator to socket Y1, providing a Master Timing Clock for the system.
• Install a jumper to J11 at the OSC position to enable the OSC drive buffer.
• Connect power supply common to the GND binding post. Connect +5 V, +12 V and -12 V to the binding
posts as marked on the board silkscreen
This configuration provides a completely operational 24-bit Analog-to-Digital-Converter evaluation system. The
CS5364 is operating as a Master Device in Single Speed Mode with a 48 kHz sampling rate. Apply power and con-
nect analog input signals of 1 Vrms maximum (full scale) to the RCA inputs jacks. S/PDIF Digital audio data is avail-
able for evaluation at the Optical and Coaxial outputs.
3. DETAILED BOARD FEATURES
The CDB5364 Evaluation Board supports both the Stand-Alone and Control Port modes of the CS5364. An FPGA
(U2) controls digital signal routing between the CS5364, the CS8406 and the DSP I/O header. For user-friendly eval-
uation of the TDM interface, the FPGA will translate TDM data into PCM data and send it to the CS8406.
3.1 Stand-Alone Evaluation
In Stand-Alone mode, the CDB5364 runs without an external PC attached. In this mode, the FPGA controls
operation of the board by dynamically reading DIP switches (S1 and S4) after a cold power-up or a push-
button board reset. Stand-Alone mode provides the most commonly used device settings. For additional
control of the CS5364, Control Port mode is used.
In Stand-Alone mode, as the DIP switches are repositioned, the FPGA simultaneously sets the appropriate
pins on the CS5364 and CS8406 to keep them synchronized with regard to sampling speed and data for-
mat.
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