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CDB6403 PDF даташит

Спецификация CDB6403 изготовлена ​​​​«Cirrus Logic» и имеет функцию, называемую «Echo-Cancelling Codec».

Детали детали

Номер произв CDB6403
Описание Echo-Cancelling Codec
Производители Cirrus Logic
логотип Cirrus Logic логотип 

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CDB6403 Даташит, Описание, Даташиты
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CS6403
Echo-Cancelling Codec
Features
l Applicable in:
- Digital-Cellular Hands-Free Phones
- Analog-Cellular Hands-Free Phones
- Office Speaker Phones
- Desktop & Video Teleconferencing
l Echo Cancellation
- Up to 60 dB ERLE
- 512 Tap (64 ms at 8 kHz sampling rate)
- Split Mode For Two Echo Cancellers
l Serial Data/Control Interface
l On-Chip Delta-Sigma Codec
- < 1% THD, 8 Load On Output
- > 70 dB S/(N+D) on Input
- 300-3600 Hz Bandwidth (8 kHz sampling rate)
- Volume Control
- Microphone Preamp
l Automatic Gain Control (AGC)
l No Training Signals Generated
I
Description
The CS6403 is an application-specific digital signal pro-
cessor optimized for network and acoustic echo
cancellation applications. A high-quality codec is inte-
grated with the processor to provide a complete, low-
cost echo-cancellation solution.
The CS6403 is a fully independent processor that re-
quires no signal processing support to implement its
cancellation functions. Volume control, AGC, and sleep
functions are also provided.
The on-chip ADC and DAC employ over-sampling tech-
nology, which eliminates the need for complex external
anti-aliasing and reconstruction filters, further reducing
system cost.
The CS6403 has a serial interface that is compatible with
most DSPs and PCM codecs. Clock and sync lines con-
trol the transfer of serial data via the separate serial data-
in and data-out pins. Both 16-bit audio data and con-
trol/status information may be multiplexed on this serial
channel using a steering bit.
ORDERING INFORMATION
CS6403-IQ -40° to +85° C
CS6403-IL -40° to +85° C
CDB6403
44-pin TQFP
44-pin PLCC
Evaluation Board
DVDD0 1
RESERVED0 6
AVDD
CONFIG
GPIN0
GPIN1
GPIN2
GPIN3
GPOUT0
GPOUT1
SFRAME
SMASTER
UALAW
SSYNC
SCLK
SDO_1
SDI_A
SYNCOUT
DGND0
DSP
High
Pass
Control
Control
Status
A
G
C
Nonlinear
Echo
Control
Volume
Control
Echo Cancellers
A
T
Nonlinear
Echo
Control
High
Pass
T
E
N
PLL + Clock Manager
Analog I/O
A
T
T
D/A
E
N
26 dB
A/D
1 CLKIN CLKOUTSCLK_RATE0SCLK_RATE1CLK_SEL AGND0 1 NC
RESET
PVDD
SPKROUTP
SPKROUTN
PGND0
PGND1
MICIN
VCM
VREF
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
MAR ‘96
DS192PP7
1









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CDB6403 Даташит, Описание, Даташиты
CS6403
ADC CHARACTERISTICS (TA = 25 °C; All DVDD, AVDD, and PVDD = 5.0V, Digital Input Levels:
Logic 0 = 0V, Logic 1 = DVDD; Signal test frequency 1kHz, word rate (Fs) = 8kHz, audio signal measurement
bandwidth is 20Hz to 4kHz; Microphone amp gain = 0dB; SPRKOUT outputs connected to 8load; CLKIN fre-
quency = 8.192MHz; unless otherwise specified) Note 1.
Parameter
Symbol Min Typ Max Units
ADC Resolution With No Missing Codes
12 -
- bits
Instantaneous Dynamic Range
IDR 67
72
- dB
Total Harmonic Distortion at -0.5dBFS signal level
THD
-
0.01 0.05
%
Gain Drift
(Note 2)
- 150 - ppm/°C
Offset Error
- 0 2 LSB
Full Scale Input Voltage
Input Resistance
Input Capacitance
(at MICIN)
(at MICIN)
(Note 3)
(Note 2)
(Note 2)
0.85 1.0
25 -
- 15
1.1 Vp
- k
- pF
Sample Rate
Fs - 8 - kHz
Microphone Amp Gain
(switchable on/off)
24 26 28 dB
Anti-aliasing Rejection
- 30 - dB
Power Supply Rejection
(1kHz)
PSR
40
-
- dB
Frequency Response
-0.6 -
0.6 dB
Transition Band
0.45 -
0.6 Fs
Stop Band Rejection
70 -
- dB
VREF Reference Voltage Output
- 2.0 - V
VCM Voltage Output
Group Delay
constant load only, >100 k
(Note 4)
- 1.0 - V
- 1 - ms
Group Delay Variations vs. Frequency
(Note 4)
- 0.0 - µs
Notes:
1. Bench testing is done with Crystal part CXT8192 driving CLKIN, automated device testing utilizes
test system provided clock sources.
2. Guaranteed by design/characterization.
3. This is the peak input voltage (in volts) with the mic amp gain set to 0 dB. Peak-to-peak voltage is
2x peak. Input signals will be properly clipped if the peak signal is greater than full scale, but less
than 2x full scale.
4. This group-delay specification is for the ADC only; additional group delay is introduced by the
AGC and high-pass filter that is implemented on the CS6403 in software.
2 DS192PP6









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CDB6403 Даташит, Описание, Даташиты
CS6403
DAC CHARACTERISTICS (TA = 25 °C; All DVDD, AVDD, and PVDD = 5.0V, Digital Input Levels:
Logic 0 = 0V, Logic 1 = DVDD; Signal test frequency 1kHz, word rate (Fs) = 8kHz, audio signal measurement
bandwidth is 20Hz to 20kHz; Microphone amp gain = 0dB; SPRKOUT outputs connected to 8load; CLKIN fre-
quency = 8.192MHz; unless otherwise specified)
Parameter
Symbol Min
Typ Max Units
DAC Resolution
12 - - bits
DAC step size error
Instantaneous Dynamic Range (20 Hz - 20 kHz)
-
IDR 60
- ±0.5 LSB
72 - dB
Frequency Response
-0.8 - +0.6 dB
Programmable Output Level Attenuator Range
(Note 5)
-92.2
-
0 dB
Gain Step Size
- 2.49 - dB
Gain Drift
(Note 2)
- 150 - ppm/°C
VREF Reference Output Voltage
- 2.0 - V
VCM Output Voltage
constant load only, >100k
- 1.0 - V
Offset Error
- 25 50 mV
Full Scale Output Voltage
(SPKROUT pins)
Common Mode Output Voltage (SPKROUT pins)
(Note 6)
1.40 1.75 1.93 Vp
-
1.30 -
V
Total Harmonic Distortion at -0.5dBFS level, SPKROUT(Note 9) THD
-
- 0.8 %
Output Impedance SPKROUT pins
Load Impedance SPKROUT pins
Output Capacitance
- 0.4 -
8 - -
- 15 - pF
Audible Stop Band Attenuation (<20kHz)
68 - - dB
Integrated Inaudible Energy (>20kHz to 100kHz) (Note 7)
- - 30 mVrms
Power Supply Rejection
(1kHz)
PSR
40
60
- dB
Filter Transition Band
0.45 - 0.6 Fs
Group Delay
(Note 8)
- 1 - ms
Notes:
5. Attenuation settings greater than 92.2 dB will cause a full scale input signal to be completely
attenuated to zero signal level.
6. This is the peak differential output voltage. The peak-to-peak signal level on each output pin is
equal to the peak differential value.
7. Assuming an external 43.2 kHz RC output filter.
8. This group-delay specification is for the DAC only; additional group delay is introduced by the
AGC and high-pass filter that is implemented on the CS6403 in software.
9. Room temperature only.
DS192PP6
3










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