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CDB5016 PDF даташит

Спецификация CDB5016 изготовлена ​​​​«Cirrus Logic» и имеет функцию, называемую «(CDB5012 - CDB5016) Evaluation Board».

Детали детали

Номер произв CDB5016
Описание (CDB5012 - CDB5016) Evaluation Board
Производители Cirrus Logic
логотип Cirrus Logic логотип 

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CDB5016 Даташит, Описание, Даташиты
www.DataSheet4U.com
Semiconductor Corporation
CDB5012 CDB5012A
CDB5014 CDB5016
Evaluation Board for CS5012, CS5012A, CS5014,
CS5016 ADC’s
Features
General Description
Compatible with CS5012, CS5012A,
CS5014, CS5016
PC/µP-Compatible Header Connection
16-Bit Parallel Data
End-of-Conversion Output
CS, RD, and A0 Control Inputs
DIP-Switch Selectable:
Unipolar/Bipolar Input Range
Burst & Interleave Calibration Modes
Continuous Conversion
Adjustable Voltage Reference
Serial Data and Clock BNC Connections
Operation from Internally-Generated or
Externally-Supplied Master Clock
The CDB5012/4/6 is an evaluation board that eases the
laboratory characterization of any of the CS5012,
CS5012A, CS5014 and CS5016 A/D converters. The
board can be easily reconfigured to simulate any com-
bination of sampling, master clock, calibration, and input
range conditions.
The converter’s parallel output data are available at a
40 pin strip header allowing easy interfacing to PC’s or
microprocessor busses. Output data is also available in
serial form at SCLK and SDATA coaxial BNC connec-
tors.
Evaluation can also be performed over a wide range of
input spans using the on-board reference circuitry. Fur-
thermore, the CDB5012, CDB5012A, CDB5014,
CDB5016 features DIP-switch selectable unipolar/bipo-
lar input ranges and the interleave calibration mode.
Calibration can be initiated at any time by momentarily
depressing a reset pushbutton.
ORDERING INFORMATION: CDB5012, CDB5012A,
CDB5014, CDB5016
AIN
HOLD
CLKIN
RESET
CS5012
CS5012A
CS5014
CS5016
A/D
Converter
D0 - D15
EOC
A0
RD
CS
SCLK
SDATA
H
E
A
D
E
R
VOLTAGE
REFERENCE
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
+5V GND -5V
Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)
MAR ’95
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CDB5016 Даташит, Описание, Даташиты
CDB5012, CDB5012A, CDB5014, CDB5016
Analog Input
The analog input to the A/D converter is supplied
through the BNC coaxial connector labeled AIN.
Analog input polarity is controlled by the first
position switch on the DIP-switch, SW-1. If it is
on, the input is unipolar ranging from GND to
VREF. If the switch is off, the input range is bi-
polar with the magnitude of the reference voltage
defining both zero- and full-scale (±VREF).
The A/D converter’s internal analog input buffer
requires a source impedance of less than 400
at 1MHz for stability. Acquisition and throughput
are specified assuming a dc source impedance of
less than 200 . Infinitely large dc source imped-
ances can be accommodated by adding capaci-
tance (typically 1000pF) from the analog input to
ground. However, high dc source resistances de-
grade acquisition time and consequently through-
put.
VA-
+ C11
+
C6
VA+
C5
VD+
R10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
EOC
CS
RD
A0
30
2
C10 SW1-4
27 25
37 EOT
R23 (optional)
3 1 HOLD
4 39 SCLK
5 40 SDATA
6 CS5012 26 AIN
7 CS5012A 20 CLKIN
8 CS5014
9 CS5016
R3
VD+
VA+
VA-
VD-
R2
R1
+5V
-5V
12 31 TST
13 C12
14 U1 28 VREF
R8 Reset
15
16
32 RESET
29 REFBUF
R9
SW2 VD+
17 C7 VA-
18
19
38 24 BP/UP
SW1-1
21 35 CAL
SW1-2
22 34 INTLV
SW1-3
23 33 BW
R4 R5 R7
36
C3
10 11
C1
R12 R13 R11 R6
VD+ + C2
VD-
+
C4
VD+
Figure 1. CDB5012, CDB5012A, CDB5014, CDB5016 Schematic
(Reference Circuitry Appears in Figure 3)
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CDB5016 Даташит, Описание, Даташиты
CDB5012, CDB5012A, CDB5014, CDB5016
Position 1
Position 2
Position 3
Position 4
OFF
ON
Bipolar
Unipolar
Burst Cal *
Normal Operation
Normal
Interleaved Cal
Normal
Continuous Conversion
* NOTE: Use of BURST CAL is not recommended.
Figure 2. DIP-Switch Definitions
Initiating Conversions
A negative transition on the converter’s HOLD
pin places the device’s analog input into the hold
mode and initiates a conversion cycle. On the
CDB5012, CDB5012A, CDB5014, CDB5016,
this input can be generated by one of two means.
First, it can be supplied through the BNC coaxial
connector appropriately labeled HOLD. Alterna-
tively, switch position 4 of the DIP-switch can be
placed in the on position, thus looping the con-
verter’s EOT output back to HOLD. This results
in continuous conversions at a fraction of the
master clock frequency (see "synchronous opera-
tion" in the converter’s data sheet).
The A/D converter’s EOT output is an indicator
of its acquisition status; it falls when the analog
input has been acquired to the specified accuracy.
If an external sampling clock is applied to the
HOLD BNC connector, care must similarly be
taken to obey the converter’s acquisition and
maximum sampling rate requirements. A more
detailed discussion of acquisition and throughput
can be found in the converter’s data sheet.
The CDB5012, CDB5012A, CDB5014,
CDB5016 is shipped from the factory without the
HOLD BNC input terminated for operation with
an external sampling clock. However, location
R23 is reserved for the insertion of a 51 resis-
tor to eliminate reflections of the incoming clock
signal.
Voltage Reference Circuitry
The CDB5012, CDB5012A, CDB5014,
CDB5016 features an adjustable voltage refer-
ence which allows characterization over a wide
range of reference voltages. The circuitry consists
of a 2.5V voltage reference (1403) and an adjust-
able gain block with a discrete output stage (Figure
3). The output stage minimizes the output’s head-
room requirements allowing the reference voltage to
come within 300mV of the positive supply.
The coarse and fine trim potentiometers are fac-
tory calibrated to a reference voltage of 4.5V (a
table of output code values for a reference volt-
age of 4.5V appears in the CS5012, CS5012A,
CS5014, CS5016 data sheets). When calibrating
the reference, the voltage should be measured di-
rectly at the VREF input (pin 28) or at the un-
grounded lead of decoupling capacitor C9.
VA+
U2
1403
R14
C13
Q1
Coarse R17
Adjust
R16
R15 -
+U3 OP-07
R18
R19
Fine
Trim
+
C8
C14 R20 R21 R22
VREF
C9
Figure 3. Voltage Reference Circuitry
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