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CDB61884 PDF даташит

Спецификация CDB61884 изготовлена ​​​​«Cirrus Logic» и имеет функцию, называемую «Octal T1/E1/J1 Line Interface Evaluation Board».

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Номер произв CDB61884
Описание Octal T1/E1/J1 Line Interface Evaluation Board
Производители Cirrus Logic
логотип Cirrus Logic логотип 

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CDB61884 Даташит, Описание, Даташиты
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CDB61884
Octal T1/E1/J1 Line Interface Evaluation Board
Features
Description
Socketed CS61884 Octal Line Interface
Unit
Binding post connectors for power and line
interface connections
Components supplied for all operational
modes E1 75 , E1 120 and T1/J1 100
Socketed termination circuitry for easy
testing
Connector for IEEE 1149.1 JTAG Boundary
Scan
LED Indicators for Loss of Signal (LOS) and
power
Supports Hardware, Serial, and Parallel
Host Modes
Easy-to-use evaluation software
On-board socketed reference clock
oscillator
The CS61884 evaluation board is used to demostrate
the functions of a CS61884 Octal Line Interface Unit in
either E1 75 , E1 120 , or T1/J1 100 applications.
The evaluation board can be operated in either Hard-
ware Mode or Host Mode. In Hardware Mode, switches
and bed stake headers are used to control the line con-
figuration and channel operations for all eight channels.
In Host Mode (Serial or Parallel), the evaluation soft-
ware, switches, and bed stake headers are used to
control the line configuration and operating mode set-
tings for each channel.
In both Hardware and Host modes, the board may be
configured for E1 75 , E1 120 Ω, or T1/J1 100 oper-
ating modes. In both modes binding post connectors
provide easy connections between the line interface
connections of the CS61884 and any E1/T1 analyzing
equipment, which may be used to evaluate the CS61884
device. Bed stake headers allow easy access to each
channel’s clock and data I/O digital interface.
Eight LED indictors display the Loss of Signal (LOS)
conditions for each channel during Hardware and Host
modes. An LED indictor is used on the Interrupt pin to
indicate a change of state.
ORDERING INFORMATION
CS61884-IQ -40° to 85° C
CDB61884
144-pin LQFP
Evaluation Board
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
©Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAR ‘02
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CDB61884 Даташит, Описание, Даташиты
CDB61884
TABLE OF CONTENTS
1. CDB61884 EVALUATION BOARD LAYOUT .......................................................................... 4
2. BOARD COMPONENT DESCRIPTIONS ................................................................................. 5
2.1 Power Connections ............................................................................................................ 5
2.2 Master Clock Selection ...................................................................................................... 5
2.3 Operating Mode Selection ................................................................................................. 6
2.4 Line Interface Connections ................................................................................................ 6
2.5 TXOE Selection ................................................................................................................. 6
2.6 Clock Edge Selection ......................................................................................................... 7
2.7 Jitter Attenuator Selection .................................................................................................. 7
2.8 Loopback Mode Selection .................................................................................................. 7
2.9 Line Length Selection ........................................................................................................ 7
2.10 Line Impedance Selection ................................................................................................ 8
2.11 Coder/Motorola/Intel Selection ......................................................................................... 8
2.12 G.772 Monitoring Address Selection ............................................................................... 8
2.13 Mux/Non-Mux/BITS Clock Selection ................................................................................ 8
2.14 Digital Signal Connections ............................................................................................... 9
2.15 LOS Indicators ................................................................................................................. 9
2.16 JTAG Connection ............................................................................................................. 9
2.17 Host Interface Connection ............................................................................................... 9
3. HOST SETUP DESCRIPTION .................................................................................................. 9
4. HOST SOFTWARE INTERFACE ............................................................................................. 9
4.1 Starting the Software ....................................................................................................... 10
4.2 Software Interface Buttons ............................................................................................... 10
4.2.1 Bit Indicator Description ...................................................................................... 10
4.3 Set All Button Description ................................................................................................ 10
4.3.1 Clear All Button Description ................................................................................ 11
4.3.2 Write All Button Description ................................................................................ 11
4.3.3 Read All Button Description ................................................................................ 11
4.4 Write Button Description .................................................................................................. 11
4.5 Read Button Description .................................................................................................. 11
4.6 Program Exit Function ..................................................................................................... 11
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT-
ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
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5. CS61884 CONFIGURATION SCREENS ............................................................................... 12
5.1 Choose Parallel Port Settings .......................................................................................... 12
5.2 Access and Configure the Read / Write Registers .......................................................... 12
5.2.1 Access Configuration Screens ............................................................................ 12
5.2.2 Select Register to Configure ............................................................................... 12
5.3 Loopback /Bits Clock Screen ........................................................................................... 13
5.4 LOS/AIS/DFM/JA Register Screen .................................................................................. 14
5.5 Transmitter Register Screen ............................................................................................ 15
5.6 AWG Register Screen ..................................................................................................... 16
5.7 Global Control Register Screen ....................................................................................... 17
6. BOARD CONFIGURATIONS ................................................................................................. 18
6.1 E1 75 Mode Setup ....................................................................................................... 18
6.2 E1 120 Mode Setup ..................................................................................................... 19
6.3 T1/J1 100 Mode Setup ................................................................................................ 20
7. EVALUATION HINTS ............................................................................................................. 21
LIST OF FIGURES
Figure 1. CDB61884 Board Layout ................................................................................................. 4
Figure 2. On-board Logic Power Selection ..................................................................................... 5
Figure 3. Master Clock Selections .................................................................................................. 5
Figure 4. Hardware/Host Mode Selection ....................................................................................... 6
Figure 5. Transmitter Enable Selection........................................................................................... 7
Figure 6. Clock Edge Selection....................................................................................................... 7
Figure 7. Jitter Attenuator Selection................................................................................................ 7
Figure 8. Loopback Mode Selection................................................................................................ 7
Figure 9. Switch S9 Settings ........................................................................................................... 8
Figure 10. Digital Signal Control/Access......................................................................................... 9
Figure 11. CDB61884 Software Opening Screen ......................................................................... 10
Figure 12. Register Bit Box ........................................................................................................... 10
Figure 13. Set All Button ............................................................................................................... 10
Figure 14. Clear All Button ............................................................................................................ 11
Figure 15. Write All Button ............................................................................................................ 11
Figure 16. Read All Button ............................................................................................................ 11
Figure 17. Write Button ................................................................................................................. 11
Figure 18. Read Button ................................................................................................................. 11
Figure 19. Opening Screen for Port and Address Selection Screen ............................................. 12
Figure 20. Loopback/G.703 Bits Clock Selection Screen ............................................................. 13
Figure 21. LOS/AIS/DFM/JA ERR Status/Enable Selection Screen ............................................. 14
Figure 22. Transmitter Register Screen ........................................................................................ 15
Figure 23. AWG Registers Screen................................................................................................ 16
Figure 24. Global Control Screen.................................................................................................. 17
LIST OF TABLES
Table 1. External Impedance Resistor Values ...................................................................................... 6
Table 2. Protection Resistor Selection ................................................................................................. 6
Table 3. Switch Settings for Host Mode ................................................................................................ 9
Table 4. E1 75 Operational Mode Switch/Jumper Position ............................................................. 18
Table 5. E1 120 Operational Mode Switch/Jumper Position ........................................................... 19
Table 6. T1/J1 100 Operational Mode Switch/Jumper Position ....................................................... 20
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