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PDF WM8987L Data sheet ( Hoja de datos )
| Número de pieza | WM8987L | |
| Descripción | Stereo CODEC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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WM8987L
Stereo CODEC for Portable Audio Applications
DESCRIPTION
The WM8987L is a low power, high quality stereo CODEC
designed for portable digital audio applications.
The device integrates complete interfaces to stereo or mono
microphones and a stereo BTL (differential) or single-ended
headset. External component requirements are reduced as
no separate microphone or headphone amplifiers are
required. Advanced on-chip digital signal processing
performs equalisation, 3-D sound enhancement and
automatic level control for the microphone or line input.
The WM8987L can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
The WM8987L operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
The WM8987L is supplied in a very small and thin 4x4mm
COL package, ideal for use in ultra-portable and wearable
systems.
BLOCK DIAGRAM
FEATURES
• DAC SNR 98dB, ADC 90dB (‘A’ weighted) at 48kHz, 3.3V
• On-chip Headphone Driver
- Single-ended or BTL (differential) drive
- >40mW output power on 16Ω / 3.3V
- DAC to 32Ω BTL headphone: SNR 86dB, THD -66dB
• Complete Stereo / Mono Microphone Interface
- Differential or single-ended mic connection
- Programmable ALC / Noise Gate
• Digital Equaliser
• Low Power
- Stereo playback 8 mW (1.8V / 1.5V supplies)
- Record and playback 13 mW (1.8V / 1.5V supplies)
• Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
• 256fs / 384fs or USB master clock rates: 12MHz, 24MHz
• Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
• 4x4mm COL package
• Register compatible with WM8750L
APPLICATIONS
• Wireless Headsets
• Portable Music Player / Recorders
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Pre-Production, January 2007, Rev 3.0
Copyright 2007 Wolfson Microelectronics plc
1 page  
Pre-Production
WM8987L
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Supply voltages
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, TA
Storage temperature after soldering
Notes
1. Analogue and digital grounds must always be within 0.3V of each other.
2. DCVDD must be less than or equal to AVDD and DBVDD.
MIN
-0.3V
DGND -0.3V
AGND -0.3V
-25°C
-65°C
MAX
+3.63V
DBVDD +0.3V
AVDD +0.3V
+85°C
+150°C
RECOMMENDED OPERATION CONDITIONS
PARAMETER
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Ground
SYMBOL
MIN
TYP
MAX
UNIT
DCVDD
1.42
3.6 V
DBVDD
1.7
3.6 V
AVDD, HPVDD
1.8
3.6 V
DGND,AGND, HPGND
0
V
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PP Rev 3.0 January 2007
5
5 Page 
Pre-Production
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
WM8987L
Figure 1 System Clock Timing Requirements
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN TYP MAX UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKL
TMCLKH
TMCLKY
21
21
54
ns
ns
ns
MCLK duty cycle
TMCLKDS
60:40
40:60
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN TYP MAX UNIT
System Clock Timing Information
MCLK System clock pulse width high
TMCLKL
10
ns
MCLK System clock pulse width low
TMCLKH
10
ns
MCLK System clock cycle time
TMCLKY
27
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
ADCLRC/
DACLRC
(Outputs)
ADCDAT
tDL
tDDA
DACDAT
tDST
tDHT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
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PP Rev 3.0 January 2007
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8987L.PDF ] | |
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