DataSheet26.com

NET2272 PDF даташит

Спецификация NET2272 изготовлена ​​​​«NetChip» и имеет функцию, называемую «USB 2.0 Peripheral Controller».

Детали детали

Номер произв NET2272
Описание USB 2.0 Peripheral Controller
Производители NetChip
логотип NetChip логотип 

70 Pages
scroll

No Preview Available !

NET2272 Даташит, Описание, Даташиты
www.DataSheet4U.com
NetChip
Technology, Inc.
335 Pioneer Way
Mt View, California 94041
(650) 526-1490 Fax (650) 526-1494
Internet: www.netchip.com
NET2272 USB 2.0 Peripheral Controller
Patent Pending
For Revision 1A
Doc #: 605-0213-0110
Revision: 1.2
Date: October 15, 2003









No Preview Available !

NET2272 Даташит, Описание, Даташиты
Specification
NET2272 USB Peripheral Controller
This document contains material that is confidential to NetChip. Reproduction without the express written consent
of NetChip is prohibited. All reasonable attempts were made to ensure the contents of this document are accurate,
however no liability, expressed or implied is guaranteed. NetChip reserves the right to modify this document,
without notification, at any time.
Revision
1.0
1.1
1.2
Issue Date
May 5, 2003
October 7, 2003
October 15, 2003
Revision History
Comments
Revision 1 silicon initial release
Revision 1.1 silicon release
Power consumption update
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
2









No Preview Available !

NET2272 Даташит, Описание, Даташиты
Specification
NET2272 USB Peripheral Controller
NET2272 USB Peripheral Controller
1 INTRODUCTION .................................................................................................................................8
1.1 FEATURES .....................................................................................................................................8
1.2 OVERVIEW ....................................................................................................................................8
1.3 NET2272 BLOCK DIAGRAM .......................................................................................................10
1.4 NET2272 TYPICAL SYSTEM BLOCK DIAGRAMS .........................................................................10
1.5 EXAMPLE CONNECTIONS TO NET2272........................................................................................12
1.5.1 Example Part Numbers..........................................................................................................13
1.5.2 General PCB Layout Guidelines ...........................................................................................13
1.5.2.1 USB Differential Signals..................................................................................................................13
1.5.2.2 Analog VDD (power).......................................................................................................................13
1.5.2.3 Analog VSS (ground).......................................................................................................................14
1.5.2.4 Decoupling Capacitors .....................................................................................................................14
1.5.2.5 EMI Noise Suppression....................................................................................................................14
1.6 TERMINOLOGY ............................................................................................................................14
2 PIN DESCRIPTION............................................................................................................................15
2.1 DIGITAL POWER & GROUND (10 PINS)........................................................................................15
2.2 USB TRANSCEIVER (15 PINS)......................................................................................................16
2.3 CLOCKS, RESET, MISC. (8 PINS)..................................................................................................17
2.4 LOCAL BUS PIN DESCRIPTIONS (31 PINS) ....................................................................................18
2.5 PHYSICAL PIN ASSIGNMENT........................................................................................................19
3 RESET AND INITIALIZATION.......................................................................................................20
3.1 OVERVIEW ..................................................................................................................................20
3.2 RESET# PIN ...............................................................................................................................20
3.3 ROOT PORT RESET ......................................................................................................................20
3.4 RESET SUMMARY ........................................................................................................................20
4 LOCAL BUS INTERFACE................................................................................................................21
4.1 INTRODUCTION............................................................................................................................21
4.2 REGISTER ADDRESSING MODES ..................................................................................................21
4.2.1 Direct Address Mode .............................................................................................................21
4.2.2 Indirect Address Mode...........................................................................................................21
4.2.3 Multiplexed Address Mode ....................................................................................................21
4.3 CONTROL SIGNAL DEFINITIONS ..................................................................................................21
4.4 BUS WIDTH / BYTE ALIGNMENT .................................................................................................21
4.5 I/O TRANSACTIONS .....................................................................................................................22
4.5.1 Non-Multiplexed I/O Read.....................................................................................................22
4.5.2 Multiplexed I/O Read.............................................................................................................22
4.5.3 Non-Multiplexed I/O Write ....................................................................................................23
4.5.4 Multiplexed I/O Write ............................................................................................................23
4.5.5 I/O Performance ....................................................................................................................24
4.5.5.1 Non-Multiplexed Read Transaction .................................................................................................24
4.5.5.2 Multiplexed Read Transaction .........................................................................................................24
4.5.5.3 Non-Multiplexed Write Transaction ................................................................................................24
4.5.5.4 Multiplexed Write Transaction ........................................................................................................24
4.6 DMA TRANSACTIONS .................................................................................................................25
4.6.1 DMA Read .............................................................................................................................25
4.6.1.1 Slow DMA Read Timing .................................................................................................................26
4.6.1.2 Fast DMA Read Timing...................................................................................................................26
4.6.1.3 Burst DMA Read Timing.................................................................................................................26
4.6.2 DMA Write.............................................................................................................................27
4.6.2.1 Slow DMA Write Timing ................................................................................................................28
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
3










Скачать PDF:

[ NET2272.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
NET2270USB 2.0 Interface ControllerNetChip
NetChip
NET2272USB 2.0 Peripheral ControllerNetChip
NetChip

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск