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GS88132B PDF даташит

Спецификация GS88132B изготовлена ​​​​«GSI» и имеет функцию, называемую «(GS88118B - GS88136B) Sync Burst SRAMs».

Детали детали

Номер произв GS88132B
Описание (GS88118B - GS88136B) Sync Burst SRAMs
Производители GSI
логотип GSI логотип 

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GS88132B Даташит, Описание, Даташиты
www.DataSheet4U.com
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
100-pin TQFP & 165-bump BGA 512K x 18, 256K x 32, 256K x 36
Commercial Temp
Industrial Temp
9Mb Sync Burst SRAMs
333 MHz150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Flow Through/Pipeline Reads
Features
The function of the Data Output register can be controlled by
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
• Byte Write (BW) and/or Global Write (GW) operation
SCD Pipelined Reads
• Internal self-timed write cycle
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
• Automatic power-down for portable applications
SCD (Single Cycle Deselect) pipelined synchronous SRAM.
• JEDEC-standard 100-lead TQFP and 165-bump BGA
DCD (Dual Cycle Deselect) versions are also available. SCD
packages
SRAMs pipeline deselect commands one stage less than read
• RoHS-compliant 100-lead TQFP and 165-bump BGA
commands. SCD RAMs begin turning off their outputs
packages available
immediately after the deselect command has been captured in
the input registers.
Functional Description
Byte Write and Global Write
Applications
Byte write operation is performed by using Byte Write enable
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
(BW) input combined with one or more individual byte write
9,437,184-bit high performance synchronous SRAM with a 2- signals (Bx). In addition, Global Write (GW) is available for
bit burst address counter. Although of a type originally
writing all bytes at one time, regardless of the Byte Write
developed for Level 2 Cache applications supporting high
control inputs.
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Controls
Memory data is retained during Sleep mode.
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
Core and Interface Voltages
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (VDDQ) pins are
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Paramter Synopsis
-333 -300 -250 -200 -150 Unit
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5 2.5 2.5 3.0 3.8 ns
3.0 3.3 4.0 5.0 6.7 ns
250 230 200 170 140 mA
290 265 230 195 160 mA
4.5 5.0 5.5 6.5 7.5 ns
4.5 5.0 5.5 6.5 7.5 ns
200 185 160 140 128 mA
230 210 185 160 145 mA
Rev: 1.05 11/2005
1/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology









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GS88132B Даташит, Описание, Даташиты
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
GS88118B 100-Pin TQFP Pinout (Package T)
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
512K x 18
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 1.05 11/2005
2/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology









No Preview Available !

GS88132B Даташит, Описание, Даташиты
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
GS88132B 100-Pin TQFP Pinout (Package T)
NC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
256K x 32
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
NC
Rev: 1.05 11/2005
3/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology










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