|
|
PDF S5933 Data sheet ( Hoja de datos )
| Número de pieza | S5933 | |
| Descripción | 32-Bit PCI MatchMaker | |
| Fabricantes | AMCC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de S5933 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
S5933
32-Bit PCI “MatchMaker”
February 12, 1997 Revised October 1998
FEATURES
• PCI 2.1 Compliant Master/Slave Device
• Full 132 Mbytes/sec Transfer Rate
• PCI Bus Operation DC to 33 Mhz
• 8/16/32 Bit Add-On User Bus
• Four Definable Pass-Thru Regions
• Two 32 Byte FIFOs
• Sync/Async Add-On Bus Operation
• Mail Box Registers w/Byte Level Status
• Direct Mail Box Data Strobe/Interrupts
• Big/Little Endian Conversions
• Direct PCI & Add-On Interrupt Pins
• Boot Loading from nvRAM or Byte Wide
• Optional Expansion BIOS/POST Code
• 160 Pin PQFP
APPLICATIONS
• High Speed Networking
• Digital Video Applications
• I/O Communications Ports
• High Speed Data Input/Output
• Multimedia Communications
• Memory Interfaces
• High Speed Data Acquisition
• Data Encryption/Decryption
• Intel i960 Interface
• General Purpose PCI Interfacing
DESCRIPTION
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing
system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places
them closer to the system’s processor bus, providing faster data transfer between the processor and peripherals. The PCI
Local bus also addresses the industry’s need for a standard that is not directly dependent on the speed, size and type of
processor bus. It represents the first microprocessor independent bus offering performance more than adequate for the
most demanding applications, such as full-motion video.
Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed and pro-
duced the S5933 to solve the problem of interfacing applications to the PCI Local bus. The S5933, or ‘Matchmaker’, is
a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can
serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5933 can
become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec.
The MatchMaker is an off-the-shelf, low-cost, standard product, which is PCI 2.1 compliant. And, since AMCC is a
member of the PCI Special Interest Group, the S5933 has been tested in "compliance workshops" along with other man-
ufacturer's PCI systems, chip sets and BIOSs. This removes the burden of compliance testing from the designer and thus
significantly reduces development time. Utilizing the S5933 allows the designer to focus on the actual application, not
debugging the PCI interface.
The MatchMaker allows special direct data accessing between the PCI bus and the user application through implemen-
tation of four definable Pass-Thru data channels. Each data channel is implemented by defining a Host memory segment
size and 8/16/32-bit user bus width. The addition of two 32 byte FIFOs, also used in S5933 Bus Mastering applications,
provides further versatility to data transfer capabilities. FIFO DMA transfers are supported using Address and Transfer
Count Registers. Four 32-bit Mailbox Registers coupled with a Status Register and extensive interrupt capabilities pro-
vide flexible user command or message transfers between the two buses. In addition, the S5933 also allows use of an
external serial, or byte-wide non-volatile memory to perform any pre-boot initialization requirements and to provide
custom expansion BIOS or POST code capability.
6290 Sequence Drive, San Diego, California 92121-4358
800-755-2622 Fax: 619-450-9885
http://www.amcc.com
1 page  
S5933
32-Bit PCI “MatchMaker”
Pass-Thru Operation
Pass-Thru operation executes PCI bus cycles in real
time with the Add-On bus. This allows the PCI bus
to directly read or write to Add-On resources. The
S5933 allows the designer to declare up to four indi-
vidual Pass-Thru Regions. Each region may be
defined as 8-, 16-, or 32-bits wide, mapped into host
memory or I/O space and may be up to 512MB bytes
in size. Figure 4 right shows a block diagram of the
S5933 Pass-Thru architecture.
S5933
Address Latch
Add-On Pass-
Thru Address
Register
Add-On Pass-Thru Write Data
Add-On Pass-Thru Read Data
Pass-Thru operations are performed in PCI target
only mode, making this data channel useful for con-
verting existing ISA or EISA designs over to the fast
Figure 4
PCI architecture. The Pass-Thru data channel uti-
lizes separate Add-On bus signal pins to reflect a
PCI bus read or write request. Add-On logic decodes these signals to determine if it must read or write data to the
S5933 to satisfy the request. Information decoded includes PCI request occurring, the byte lanes involved, the spe-
cific Pass-Thru region accessed and if the request is a burst or single-cycle access. All requested Pass-Thru address
and data information is passed via Add-On Operation Registers.
Pass-Thru operation supports single PCI data cycles and PCI data bursts. During PCI burst operations, the S5933 is
capable of transferring data at the full PCI bandwidth. Should slower Add-On logic be implemented, the S5933 auto-
matically issues PCI bus waits or a Host retry indication until the requested transfer is satisfied.
FIFO PCI Bus Mastering Operation
FIFO PCI Bus Master data transfers are processed by one of two 8-DWORD FIFOs. The FIFO block diagram is
shown in Figure 5. The particular FIFO selected for a data transfer is dependent only on the direction of data flow and
is completely transparent to the user. Internal S5933 decode logic selects the FIFO that is dedicated to transferring
data to the other bus.
The way data is transferred by a FIFO, is determined by Operation and Configuration Registers contained within the
S5933. A FIFO may be configured for either PCI or Add-On initiated Bus Mastering with programmable byte
advance conditions, read vs. write priorities and Add-On bus widths. Advance conditions allow the FIFO to imple-
ment 8-, 16- or 32-bit bus widths. Configuring the S5933 for Bus Master operation enables separate address and data
count registers, which are loaded with the PCI memory address location and number of bytes to be read or written.
This is accomplished by either the Host CPU or Add-On logic. Data can be transferred between the two buses trans-
parent to the PCI Host processor, however, the Add-On logic is required to service the S5933 Add-On Local bus. An
indication of transfer completion can be seen by polling a status register done bit or S5933 signal pin or enabling a
'transfer count = 0' interrupt to either bus.
Further FIFO configuration bits select 16, 32, or 64 bit Endian conversion options for incoming and outgoing data.
Endian conversion allows an Add-On processor and the host to transfer data in their native Endian format. Other con-
figuration bits determine if the Add-On Local bus width is 8, 16 or 32 bits. 16-bit bus configurations internally steer
FIFO data from the upper 16 bits of the DWORD and then to the lower 16-bits on alternate accesses. FIFO pointers
are then updated when appropriate bytes are accessed. Other methods are available for 8-bit or 16-bit Add-Ons.
Efficient FIFO management configuration schemes unique to the AMCC S5933 specify how full or empty a FIFO
must be before it requests the PCI Local bus. These criteria include bus requests when any of the 8 DWORDs are
empty, or when four or more DWORDs are empty. This allows the designer to control how often the S5933 requests
the bus. The S5933 always attempts to perform burst operations to empty or fill the FIFOs. Further FIFO capabilities
over the standard register access methods allow for direct hardware FIFO access. This is provided through separate
access pins on the S5933. Other status output pins allow for easily cascading external FIFOs to the Add-On design.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
5
5 Page 
S5933
32-Bit PCI “MatchMaker”
TIMING DIAGRAMS
Synchronous RDFIFO# Timing
BPCLK
RDFIFO#
DQ[31:0]
RDEMPTY
FRF
1
Old Valid
2
34
New Valid
Notes:
1. The data 1 valid time is dependent on where RDFIFO# is asserted in it's window.
2. The data 4 signal is cut short due to the de-assertion of RDFIFO#.
3. The RDEMPTY is an example relative to data 2, if the FIFO went empty on data 2.
Synchronous WRFIFO# Timing
BPCLK
WRFIFO#
DQ[31:0]
WRFULL
FWE
12
Old Valid
3
New Valid
Notes:
1. The WRFULL is an example relative to data 2, if data 2 were to fill the FIFO.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet S5933.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| S5930 | NMOS multichannel detector head |  Hamamatsu Corporation |
| S5930-256S | NMOS multichannel detector head | Hamamatsu Corporation |
| S5930-512S | NMOS multichannel detector head | Hamamatsu Corporation |
| S5931 | NMOS multichannel detector head | Hamamatsu Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |