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Спецификация S1L50000 изготовлена «Epson» и имеет функцию, называемую «HIGH DENSITY GATE ARRAY». |
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Детали детали
Номер произв | S1L50000 |
Описание | HIGH DENSITY GATE ARRAY |
Производители | Epson |
логотип |
12 Pages
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DATA SHEET
ASIC
S1L50000
S1L50000 SERIES HIGH DENSITY GATE ARRAY
DESCRIPTION
EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS
gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V
tolerant I/O buffers.
• Ultra-high-speed, high density and low power consumption
• Low voltage operation: 3.3V and 2.0V
• Number of raw gates: 28,710 ~ 815,468 gates
FEATURES
• Process
0.35µm 2/3/4 layer metalization CMOS process
• Integration
A maximum of 815,468 gates (2 input NAND gate equivalent)
• Operating Speed
• I/F Levels
Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ)
(2-input pair NAND, F/O = 2, Typical wire load)
Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used.
400 ps (3.3V Typ), 1.30 ns (2.0V Typ)
(F/O = 2, Typical wire load)
Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used.
2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ)
(CL = 15 pF)
Input/Output TTL/CMOS/LVTTL compatible
• Input Modes
TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI
Built-in pull-up and pull-down resistors can be usable.
(2 types for each resistor value)
• Output Modes
Normal, 3-state, bi-directional, PCI
• Output Drive
• RAM
IOL = 0.1, 1, 3, 8, 12, 24 mA selectable
(Built-in level shifter is used at 5.0V)
IOL = 0.1, 1, 2, 6, 12 mA selectable (at 3.3V)
IOL = 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V)
Asynchronous 1-port, asynchronous 2-port
• Dual Power
Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage
I/O Buffer: Built-in interfaces of both high and low voltages possible
• Operation possible at VDD = 2.0 ± 0.2V
i i i iEPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
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DATA SHEET
ASIC
S1L50000
LINE UP
The S1L50000 Series comprises 11 types of masters, from which the customer is able to select
the master most suitable.
Total
Number
Number
Number Cell Utilization Ratio (U)*1
Master
BC of of of 2-layer 3-layer 4-layer
(Raw Gates) Pads Columns (X) Rows (Y) metal metal metal
S1L50282/283/284
28710
88
319
90
50% 88%
95%
S1L50752/753/754
75774
144
519
146
47% 85%
95%
S1L50992/993/994
99198
168
594
167
47% 85%
95%
S1L51252/253/254
125772
188
669
188
45% 80%
95%
S1L51772/773/774
177062
224
794
223
45% 75%
95%
S1L52502/503/504
250160
264
944
265
45% 75%
95%
S1L53352/353/354
335858
308
1094
307
43% 75%
95%
S1L54422/423/424
442112
352
1256
352
40% 70%
90%
S1L55062/063/064
506688
376
1344
377
40% 70%
90%
S1L56682/683/684
668552
432
1544
433
40% 70%
90%
S1L58152/153/154
815468
480
1706
478
40% 70%
90%
NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of
the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only
as an estimate
i i i i2 EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
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DATA SHEET
ASIC
S1L50000
ELECTRICAL CHARACTERISTICS AND SPECIFICATIONS
Absolute Maximum Ratings (For Single Power Supply):
(Vss = 0V)
Item
Symbol
Limits
Unit
Power Supply Voltage
Input Voltage
Output Voltage
Output Current/Pin
VDD
VI
VO
IOUT
-0.3 to 4.0
-0.3 to VDD + 0.5*1
-0.3 to VDD + 0.5*1
± 30
V
V
V
mA
Storage Temperature
TSTG
-65 to 150
°C
*1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH
systems.
Absolute Maximum Ratings (For Dual Power Supplies):
Item
Power Supply Voltage
Symbol
HVDD
Limits
-0.3 to 7.0
(Vss = 0V)
Unit
V
Input Voltage
Output Voltage
LVDD
HVI
LVI
HVO
LVO
-0.3 to 4.0
-0.3 to HVDD + 0.5*1
-0.3 to LVDD + 0.5*1
-0.3 to HVDD + 0.5*1
-0.3 to LVDD + 0.5*1
V
V
V
V
V
Output Current/Pin
IOUT
± 30 (± 50 *2)
mA
Storage Temperature
TSTG
-65 to 150
°C
**1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH
systems.
*2: Possible to use for 24mA of output buffer.
i i i iEPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
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Номер в каталоге | Описание | Производители |
S1L50000 | HIGH DENSITY GATE ARRAY | Epson |
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