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PDF 74LVC132A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC132A | |
| Descripción | Quad 2-Input NAND Schmitt Trigger | |
| Fabricantes | NXP Semiconductors | |
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74LVC132A
Quad 2-input NAND Schmitt trigger
Rev. 01 — 15 December 2006
Product data sheet
1. General description
The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT− is defined as the input
hysteresis voltage VH.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V environment.
2. Features
s Wide supply voltage range from 2.3 V to 3.6 V
s 5 V tolerant inputs for interfacing with 5 V logic
s CMOS low power consumption
s Direct interface with TTL levels
s Unlimited rise and fall times
s Inputs accept voltages up to 5.5 V
s Complies with JEDEC standard JESD8-B/JESD36
s ESD protection:
x HBM JESD22-A114-D exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
s Wave and pulse shaper
s Astable multivibrator
s Monostable multivibrator.
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NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ[1]
Tamb = −40 °C to +85 °C
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 3.6 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VCC − 0.2 -
VCC − 0.45 -
VCC − 0.5 -
VCC − 0.5 -
VCC − 0.6 -
VCC − 0.8 -
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 3.6 V
-
-
IO = 4 mA; VCC = 1.65 V
--
IO = 8 mA; VCC = 2.3 V
--
II
ICC
∆ICC
input leakage current
supply current
additional supply current
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 5.5 V or GND
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
per input pin; VCC = 2.7 V to 3.6 V;
VI = VCC − 0.6 V; IO = 0 A
-
-
-
-
-
-
-
±0.1
0.1
5
CI input capacitance
Tamb = −40 °C to +125 °C
VCC = 0 V to 3.6 V; VI = GND to VCC
-
4.0
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 3.6 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VCC − 0.3 -
VCC − 0.6 -
VCC − 0.65 -
VCC − 0.65 -
VCC − 0.75 -
VCC − 1 -
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 3.6 V
-
-
IO = 4 mA; VCC = 1.65 V
--
IO = 8 mA; VCC = 2.3 V
--
IO = 12 mA; VCC = 2.7 V
--
IO = 24 mA; VCC = 3.0 V
--
II input leakage current VCC = 3.6 V; VI = 5.5 V or GND
--
ICC
∆ICC
supply current
additional supply current
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
per input pin; VCC = 2.7 V to 3.6 V;
VI = VCC − 0.6 V; IO = 0 A
-
-
-
-
Max
-
-
-
-
-
-
0.2
0.45
0.6
0.4
0.55
±5
10
500
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
±20
40
5
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
pF
V
V
V
V
V
V
V
V
V
V
V
µA
µA
mA
74LVC132A_1
Product data sheet
Rev. 01 — 15 December 2006
© NXP B.V. 2006. All rights reserved.
5 of 15
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NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
y
Z
14
8
c
EA
X
HE v M A
pin 1 index
1
e
7
bp
wM
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
5.1
4.9
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT402-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13 0.1
0.72
0.38
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 12. Package outline SOT402-1 (TSSOP14)
74LVC132A_1
Product data sheet
Rev. 01 — 15 December 2006
© NXP B.V. 2006. All rights reserved.
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