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PDF W39V040A Data sheet ( Hoja de datos )
| Número de pieza | W39V040A | |
| Descripción | 512K X 8 CMOS FLASH MEMORY | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W39V040A
512K × 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
1. GENERAL DESCRIPTION
The W39V040A is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For
flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased
in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture
of the W39V040A results in fast program/erase operations with extremely low current consumption. This
device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in
the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs.
But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also
be programmed and erased using standard EPROM programmers.
2. FEATURES
• Single 3.3-volt Operations:
− 3.3-volt Read
− 3.3-volt Erase
− 3.3-volt Program
• Fast Program Operation:
− Byte-by-Byte programming: 35 µS (typ.)
• Fast Erase Operation:
− Chip erase 100 mS (max.)
− Sector erase 25 mS (max.)
− Page erase 25 mS (max.)
• Fast Read access time: Tkq 11 nS
• Endurance: 10K cycles (typ.)
• Twenty-year data retention
• 8 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
• Any individual sector or page can be erased
• Hardware protection:
− Optional 16K byte or 64K byte Top Boot Block
with lockout protection
− #TBL & #WP support the whole chip hardware
protection
• Flexible 4K-page size can be used as Parameter
Blocks
• Low power consumption
− Active current: 12.5 mA (typ. for LPC mode)
• Automatic program and erase timing with
internal VPP generation
• End of program or erase detection
− Toggle bit
− Data polling
• Latched address and data
• TTL compatible I/O
• Available packages: 32L PLCC, 32L STSOP
Publication Release Date: December 19, 2002
- 1 - Revision A2
1 page  
W39V040A
Hardware Data Protection
The integrity of the data stored in the W39V040A is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation is inhibited when VDD is less
than 1.5V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the devices will automatically time-out 5
mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W39V040A includes a data polling feature to indicate the end of a program or erase cycle. When
the W39V040A is in the internal program or erase cycle, any attempts to read DQ7 of the last byte
loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7
will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical
"1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W39V040A provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Multi-Chip Operation
Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up to
16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond
W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for
registers memory space.
Register
There are two kinds of registers on this device, the General Purpose Input Registers and Product
Identification Registers. Users can access these registers through respective address in the 4Gbytes
memory map. There are detail descriptions in the sections below.
General Purpose Inputs Register
This register reads the states of GPI[4:0] pins on the W39V040A. This is a pass-through register, which
can be read via memory address FFBxE100(hex). The "x" in the addresses represents the ID [3:0] pin
straps. Since it is pass-through register, there is no default value.
Publication Release Date: December 19, 2002
- 5 - Revision A2
5 Page 
W39V040A
Embedded #Data Polling Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = VA
No DQ7 = Data
?
Yes
Pass
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during sector
erase operation
= Any of the page addresses within
the sector being erased during page
erase operation
= Any of the device addresses within
the chip being erased during chip
erase operation
Embedded Toggle Bit Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = Don't Care
No
DQ6 = Toggle
?
Yes
Fail
- 11 -
Publication Release Date: December 19, 2002
Revision A2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W39V040A.PDF ] | |
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