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PDF NTMD2P01R2 Data sheet ( Hoja de datos )
| Número de pieza | NTMD2P01R2 | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTMD2P01R2
Power MOSFET
−2.3 Amps, −16 Volts
Dual SOIC−8 Package
Features
• High Efficiency Components in a Single SOIC−8 Package
• High Density Power MOSFET with Low RDS(on)
• Logic Level Gate Drive
• SOIC−8 Surface Mount Package,
Mounting Information for SOIC−8 Package Provided
• Pb−Free Packages are Available
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance − Junction−to−Ambient
(Note 3)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
Operating and Storage
Temperature Range
VDSS
VGS
−16
"10
V
V
RPqDJA
ID
ID
IDM
175
0.71
−2.3
−1.45
−9.0
°C/W
W
A
A
A
RPqDJA
ID
IDIDM
105
1.19
−2.97
−1.88
−12
°C/W
W
A
A
A
RPqDJA
ID
ID
IDM
TJ, Tstg
62.5
2.0
−3.85
−2.43
−15
−55 to
+150
°C/W
W
A
A
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = −16 Vdc, VGS = −4.5 Vdc, Peak IL
= −5.0 Apk, L = 28 mH, RG = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS
TL
350 mJ
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), Steady State.
3. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
VDSS
−16 V
RDS(ON) Typ
100 mW @ −4.5 V
ID Max
−2.3 A
P−Channel
D
G
8
1
SOIC−8
SUFFIX NB
CASE 751
STYLE 11
S
MARKING DIAGRAM*
AND PIN ASSIGNMENT
D1 D1 D2 D2
8
ED2P01
AYWW G
G
1
S1 G1 S2 G2
ED2P01= Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
NTMD2P01R2
NTMD2P01R2G
Package
Shipping†
SOIC−8 2500/Tape & Reel
SOIC−8 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 2
1
Publication Order Number:
NTMD2P01R2/D
1 page  
1
D = 0.5
NTMD2P01R2
0.2
0.1 0.1
0.05
0.02
0.01
Single Pulse
0.01
1E−03
1E−02
Normalized to R∅ja at Steady State (1 inch pad)
0.0125 W 0.0563 W 0.110 W 0.273 W 0.113 W 0.436 W
0.021 F 0.137 F 1.15 F 2.93 F 152 F
261 F
1E−01
1E+00
t, TIME (s)
1E+03
Figure 13. FET Thermal Response
1E+02
1E+03
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NTMD2P01R2.PDF ] | |
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