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ZL38010 PDF даташит

Спецификация ZL38010 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «Low Power Quad ADPCM Transcoder».

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Номер произв ZL38010
Описание Low Power Quad ADPCM Transcoder
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

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ZL38010 Даташит, Описание, Даташиты
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ZL38010
Low Power Quad ADPCM Transcoder
Data Sheet
Features
• Full duplex transcoder with four encode channels
and four decode channels
• 32 kbps, 24 kbps and 16 kbps ADPCM coding
complying with ITU-T (previously CCITT) G.726
(without 40 kbps), and ANSI T1.303-1989
• Low power operation, 6.5 mW typical
• Asynchronous 4.096 MHz master clock operation
• SSI and ST-BUS interface options
• Transparent PCM bypass
• Transparent ADPCM bypass
• Linear PCM code
• No microprocessor control required
• Simple interface to Codec devices
• Pin selectable µ−Law or A-Law operation
• Pin selectable ITU-T or signed magnitude PCM
coding
• Single 3.3 Volts power supply
January 2007
Ordering Information
ZL38010DCE 28 Pin SOIC
ZL38010DCF 28 Pin SOIC
ZL38010DCE1 28 Pin SOIC**
ZL38010DCF1 28 Pin SOIC**
**Pb Free Matte Tin
-40°C to +85°C
Tubes
Tape & Reel
Tubes
Tape & Reel
Applications
• Pair gain
• Voice mail systems
• Wireless telephony systems
Description
The Quad ADPCM Transcoder is a low power, CMOS
device capable of four encode and four decode
functions per frame. Four 64 kbps PCM octets are
compressed into four 32, 24 or 16 kbps ADPCM words,
and four 32, 24 or 16 kbps ADPCM words are
expanded into four 64 kbps PCM octets. The 32, 24
and 16 kbps ADPCM transcoding algorithms utilized
conform to ITU-T Recommendation G.726 (excluding
40 kbps), and ANSI T1.303 - 1989.
ADPCMi
ADPCMo
ENB1
ENB2/F0od
BCLK
F0i
MCLK
C2o
EN1
EN2
ADPCM
I/O
Full Duplex
Quad
Transcoder
PCM
I/O
PCMo1
PCMi1
PCMo2
PCMi2
Timing
Control Decode
VDD VSS PWRDN IC
MS1 MS2 MS3 A/µ FORMAT MS4 MS5 MS6 LINEAR SEL
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved.









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ZL38010 Даташит, Описание, Даташиты
ZL38010
Data Sheet
Switching, on-the-fly, between 32 kbps and 24 kbps ADPCM, is possible by controlling the appropriate mode select
(MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to
industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to
facilitate external DSP functions.
Change Summary
Changes from October 2005 Issue to January 2007 Issue.
Page
1
Item
Ordering Information Box
Change
Added Pb Free part numbers.
EN1
MCLK
F0i
C2o
BCLK
PCMo1
PCMi1
VSS
LINEAR
ENB2/F0od
ENB1
PCMo2
PCMi2
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 EN2
27 MS6
26 MS5
25 MS4
24 ADPCMo
23 ADPCMi
22 VDD
21 MS3
20 MS2
19 MS1
18 IC
17 PWRDN
16 FORMAT
15 A/µ
Pin Description
Pin #
Name
1 EN1
2 MCLK
3 F0i
4 C2o
Figure 2 - Pin Connections
Description
Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1
PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1.
In SSI mode this output is high impedance.
Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the
transcoder function; it must be supplied in both ST-BUS and SSI modes of operation.
In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is
also used to control the data I/O flow on the PCM and ADPCM input/output pins
according to ST-BUS requirements.
In SSI mode this master clock input is derived from an external source and may be
asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are
acceptable in this mode since the data I/O rate is governed by BCLK.
Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI
operation is enabled by connecting this pin to VSS.
2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input
divided by two, inverted, and synchronized to F0i. This output is high-impedance during
SSI operation.
2
Zarlink Semiconductor Inc.









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ZL38010 Даташит, Описание, Даташиты
ZL38010
Data Sheet
Pin #
5
6
7
8
9
10
11
12
13
14
Name
Description
BCLK
Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports;
used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1
and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input
must be tied to VSS for ST-BUS operation.
PCMo1
Serial PCM Stream 1 (Output). 128 kbps to 4096 kbps serial companded/linear PCM out-
put stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by
MCLK divided by two in ST-BUS mode. See Figure 14.
PCMi1
Serial PCM Stream 1 (Input). 128 kbps to 4096 kbps serial companded/linear PCM
input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
VSS
LINEAR
ENB2/F0od
Digital Ground. Nominally 0 volts
Linear PCM Select (Input). When tied to VDD the PCM I/O ports (PCM1,PCM2) are 16-
bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbps. Companded PCM is
selected when this pin is tied to VSS. See Figure 5 & Figure 8.
PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output).
SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel
(AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See
Figure 4 & Figure 6.
ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LIN-
EAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles after
F0i and when LINEAR = 1 at 128 C4 clock cycles after F0i. See Figures 7, 8, 9 & 14.
ENB1
PCM B-Channel Enable Strobe 1 (Input).
SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. A
valid 8-bit strobe must be present at this input for SSI operation.
ST-BUS operation: When tied to VSS transparent bypass of the ST-BUS D- and C- chan-
nels is enabled. When tied to VDD the ST-BUS D-channel and C-channel output timeslots
are forced to a high-impedance state.
PCMo2
PCMi2
Serial PCM Stream 2 (Output). 128 kbps to 4096 kbps serial companded/linear PCM out-
put stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divid-
ed by two in ST-BUS mode. See Figure 14.
Serial PCM Stream 2 (Input). 128 kbps to 4096 kbps serial companded/linear PCM input
stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
SEL SELECT (Input).
PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operation
and when SEL=1 the PCM2 port is selected for PCM bypass operation.
See Figure 6 & Figure 9.
16 kbps transcoding mode:
SSI Operation - in 16 kbps transcoding mode, the ADPCM words are assigned to the I/O
timeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4.
ST-BUS operation- in 16 kbps transcoding mode, the ADPCM words are assigned to the
B2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.
3
Zarlink Semiconductor Inc.










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Номер в каталогеОписаниеПроизводители
ZL38010Low Power Quad ADPCM TranscoderZarlink Semiconductor
Zarlink Semiconductor

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