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ZL50058 PDF даташит

Спецификация ZL50058 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «(ZL50057 / ZL50058) 12 K-Channel Digital Switch».

Детали детали

Номер произв ZL50058
Описание (ZL50057 / ZL50058) 12 K-Channel Digital Switch
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

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ZL50058 Даташит, Описание, Даташиты
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ZL50057/8
12 K-Channel Digital Switch with High Jitter
Tolerance, Per Stream Rate Conversion (2, 4, 8,
16, or 32 Mbps), and 48 Inputs and 48 Outputs
Data Sheet
Features
• 12,288-channel x 12,288-channel non-blocking
unidirectional switching.The Backplane and Local
inputs and outputs can be combined to form a
non-blocking switching matrix with 48 input
streams and 48 output streams
• 8,192-channel x 4,096-channel non-blocking
Backplane input to Local output stream switch
• 4,096-channel x 8,192-channel non-blocking
Local input to Backplane output stream switch
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
• 4,096-channel x 4,096-channel non-blocking
Local input to Local output stream switch
• Rate conversion on all data paths, Backplane-to-
Local, Local-to-Backplane, Backplane-to-
Backplane and Local-to-Local streams
• Backplane port accepts 32 input and 32 output
ST-BUS streams with data rates of 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 16 input and
16 output streams at 32.768 Mbps
• Local port accepts 16 input and 16 output ST-
BUS streams with data rates of 2.048 Mbps,
January 2006
Ordering Information
ZL50057GAC 272-Ball PBGA
ZL50058GAC 256 Ball PBGA
ZL50058GAG2 256 Ball PBGA**
**Pb Free Tin/Silver/Copper
-40°C to +85°C
Trays
Trays
Trays
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 8 input and 8
output streams at 32.768 Mbps
• Exceptional input clock jitter tolerance (17 ns for
16 Mbps or lower data rates, 14 ns for 32 Mbps)
• Per-stream channel and bit delay for Local and
Backplane input streams
• Per-stream advancement for Local and
Backplane output streams
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-31
Backplane Data Memories
(8,192 channels)
Local
Interface
LSTi0-15
BSTo0-31
BCST0-3
BORS
FP8i
C8i
Backplane
Interface
Backplane
Connection Memory
(8,192 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
Input
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LSTo0-15
LCST0-1
LORS
FP8o
FP16o
C8o
C16o
VDD_PLL
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50057/8 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.









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ZL50058 Даташит, Описание, Даташиты
ZL50057/8
• High impedance-control outputs for external drivers on Local and Backplane ports
• Per-channel message mode for Local and Backplane output streams
• Connection memory block programming for fast device initialization
• BER testing for Local and Backplane ports
• Automatic selection between ST-BUS and GCI-Bus operation
• Non-multiplexed Motorola microprocessor interface
• Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
• Memory Built-In-Self-Test (BIST), controlled via microprocessor register
• 1.8 V core supply voltage
• 3.3V I/O supply voltage
• 5 V tolerant inputs, outputs and I/Os
• ZL50057 is pin-to-pin compatible with Zarlink’s MT90870 device 1
Note 1: For software compatibility between ZL50057 and MT90870, please refer to Section 2.6.
Applications
• Central Office Switches (Class 5)
• Media Gateways
• Class-independent switches
• Access Concentrators
• Scalable TDM-Based Architectures
• Digital Loop Carriers
Data Sheet
2
Zarlink Semiconductor Inc.









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ZL50058 Даташит, Описание, Даташиты
ZL50057/8
Data Sheet
Device Overview
The ZL50057 and ZL50058 are two different packages of the same device. The ZL50057/8 has two data ports, the
Backplane and the Local port. The Backplane port has two independent modes of operation, either 32 input and 32
output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any combination, or 16 input
and 16 output streams operated at 32.768 Mbps. The Local port has two independent modes of operation, either 16
input and 16 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any
combination, or 8 input and 8 output streams operated at 32.768 Mbps.
The ZL50057/8 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
• Input-to-Output Unidirectional, supporting 12 K x 12 K switching
• Backplane-to-Local Bi-directional, supporting 8 K x 4 K data switching,
• Local-to-Backplane Bi-directional, supporting 4 K x 8 K data switching,
• Backplane-to-Backplane Bi-directional, supporting 8 K x 8 K data switching.
• Local-to-Local Bi-directional, supporting 4 K x 4 K data switching.
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
In Connection Mode, the contents of the connection memory define, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-
Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period, the input frame pulse format is determined before
switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of
the Backplane and Local ports.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control
signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The ZL50057 and ZL50058 are each available in one package:
• ZL50057: a 27 mm x 27 mm body, 1.27mm ball-pitch, 272-PBGA.
• ZL50058: a 17 mm x 17 mm body, 1mm ball-pitch, 256-PBGA.
3
Zarlink Semiconductor Inc.










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