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PDF ZL50063 Data sheet ( Hoja de datos )
| Número de pieza | ZL50063 | |
| Descripción | 16K-Channel Digital Switch | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL50063
16K-Channel Digital Switch with High Jitter
Tolerance, Single Rate (32Mbps),
and 32 Inputs and 32 Output
Data Sheet
Features
• 16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and Local
inputs and outputs can be combined to form a
non-blocking switching matrix with 32 input
streams and 32 output streams
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Local output stream switch
• 8,192-channel x 8,192-channel non-blocking
Local input to Backplane output stream switch
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
• 8,192-channel x 8,192-channel non-blocking
Local input to Local output stream switch
• Backplane port accepts 16 input and 16 output
ST-BUS streams with data rate of 32.768Mbps
• Local port accepts 16 input and 16 output ST-
BUS streams with data rate of 32.768Mbps
• Exceptional input clock jitter tolerance (14ns)
• Per-stream bit delay for Local and Backplane
input streams
• Per-stream advancement for Local and
Backplane output streams
November 2003
Ordering Information
ZL50063GAC 196-Ball PBGA
-40°C to +85°C
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
• Per-channel message mode for Local and
Backplane output streams
• Connection memory block programming for fast
device initialization
• Automatic selection between ST-BUS and GCI-
Bus operation
• Non-multiplexed Motorola microprocessor
interface
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-15
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-15
BSTo0-15
Backplane
Interface
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
LSTo0-15
BORS
FP8i
C8i
Input
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LORS
FP8o
FP16o
C8o
C16o
VDD_PLL
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50063 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL50063
Data Sheet
Table of Contents
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13.3 Local Input Bit Delay Registers (LIDR0 to LIDR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.5 Local Output Advancement Registers (LOAR0 to LOAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.6 Backplane Output Advancement Registers (BOAR0 - BOAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.8 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5
Zarlink Semiconductor Inc.
5 Page 
ZL50063
Data Sheet
Pin Description (continued)
Pin Name
ZL50063
Package
Coordinates
(196-ball
PBGA)
Description
BSTo8-15
C3, F1, D3, E2,
E1, E3, F2, F3
Backplane Serial Output Streams 8 to 15 (5V Tolerant, Three-state
Outputs with Slew-Rate Control).
These pins output serial TDM data streams at a fixed data rate of
32.768Mbps (with 512 channels per stream).
Refer to the descriptions of the BORS and ODE pins for control of the output
HIGH or high impedance state.
LORS
H13 Local Output Reset State (5V Tolerant Input with Internal Pull-down).
When this input is LOW, the device will initialize with the LSTo0-15 outputs
driven high. Following initialization, the Local stream outputs are always
active.
When this input is HIGH, the device will initialize with the LSTo0-15 outputs at
high impedance. Following initialization, the Local stream outputs may be set
active or high impedance using the ODE pin or on a per-channel basis with
the LE bit in the Local Connection Memory.
LSTo0-7
B13, B14, D14,
C14, D12, E14,
D13, E13
Local Serial Output Streams 0 to 7 (5V Tolerant Three-state Outputs with
Slew-Rate Control).
These pins output serial TDM data streams at a fixed data rate of
32.768Mbps (with 512 channels per stream).
Refer to the descriptions of the LORS and ODE pins for control of the output
HIGH or high impedance state.
LSTo8-15
E12, F14, G14,
G12, F12, F13,
H14, G13
Local Serial Output Streams 8 to 15 (5V Tolerant Three-state Outputs
with Slew-Rate Control).
These pins output serial TDM data streams at a fixed data rate of
32.768Mbps (with 512 channels per stream).
Refer to the descriptions of the LORS and ODE pins for control of the output
HIGH or high impedance state.
Microprocessor Port Signals
A0 - A14
B1, B4, B5, D5,
A3, A4, C6, B6,
A5, A6, C7, B7,
A7, A8, B8
Address 0 - 14 (5V Tolerant Inputs). These pins form the 15-bit address bus
to the internal memories and registers.
A0 = LSB
D0 - D15
N7, P7, P6, N6,
P5, M6, P4, N5,
P3, P2, N3, N4,
M5, N2, M4, M3
Data Bus 0 - 15 (5V Tolerant Inputs/Outputs with Slew-Rate Control).
These pins form the 16-bit data bus of the microprocessor port.
D0 = LSB
CS A10 Chip Select (5V Tolerant Input). Active LOW input used by the
microprocessor to enable the microprocessor port access. Note that a
minimum of 30ns must separate the de-assertion of DTA (to high) and
the assertion of CS and/or DS to initiate the next access.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 60 Páginas | |
| PDF Descargar | [ Datasheet ZL50063.PDF ] | |
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