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PDF ZL50211 Data sheet ( Hoja de datos )
| Número de pieza | ZL50211 | |
| Descripción | 256 Channel Voice Echo Canceller | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL50211
256 Channel Voice Echo Canceller
Data Sheet
Features
• ZL50211 has eight Echo Voice Processors in a
single BGA package. This single device provides
256 channels of 64 msec echo cancellation or
128 channels at 128 msec echo cancellation
• Each Echo Voice Processor has the capability of
cancelling echo over 32 channels
• Each Echo Voice Processor (EVP) shares the
address bus and data bus with each other
• Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
• Passed all AT&T voice quality tests for carrier
grade echo canceller
• The ZL50211 provides more than 58% board
space savings when compared with the eight
Echo Voice Processors packaged devices
• Each EVP has a Patented Advanced Non-Linear
Processor with high quality subjective
performance
• Each EVP has protection against narrow band
signal divergence and instability in high echo
environments
January 2006
Ordering Information
ZL50211GBC 535 Ball BGA Trays
ZL50211GBG2 535 Ball BGA** Trays
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Each EVP can be programmed independently in
any mode e.g., Back-to-Back or Extended Delay
to provide capability of cancelling different echo
tails
• Each EVP has 0 to -12 dB level adjusters at all
signal ports (Rin, Sin, Sout and Rout)
• Each EVP has the same JTAG identification code
Applications
• Voice over IP network gateways
• Voice over ATM, Frame Relay
• T1/E1/J1 multichannel echo cancellation
• Wireless base stations
• Echo Canceller pools
• DCME, satellite and multiplexer system
Rin1...Rin8
Sin1....Sin8
D0....D7
CS1..CS8
A0..A12
RESET1..RESET8
ZL50211GB
EVP1
EVP2
EVP3
EVP4
EVP5
EVP6
EVP7
EVP8
Rout1..Rout8
Sout1..Sout8
IRQ1..IRQ8
DTA1..DTA8
Figure 1 - ZL50211 Device Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
Pin Description
Signal
Name
VDD1 = 3.3V
(VDD_IO)
Signal
Type
Power
VDD2 = 1.8V
(VDD_Core)
Power
VSS
Power
TE1, TE2,
TE3, TE4,
TE5, TE6,
TE7, TE8
Test Mode
Pins
OUTPUT
TEST PINS
Test
pins
ZL50211
Data Sheet
BGA Ball #
Signal
Description
AC5,AC26,AC27,AD26,AD5,AE5,AF12,AF13,AF1 Positive Power
4,AF17,AF18,AF19,AF24,AF6,AF7,AF8,AG24,AH Supply. Nominally
24,E13,E14,E17,E18,E19,E23,E24,E25,E6,E7,E8, 3.3 volt (I/O
F5,G26,G27,G5,H26,H5,M26,M5,N26,N5,P26,P27 voltage).
, P4,P5,U26,U27,U4,U5,V26,V5,W26,W5
AA26,AA28,AA3,AA5,AB26,AB28,AB3,AB5,AF11, Positive Power
AF20,AG10,AG21,AG22,AH10,AH11,AH22,AJ15, Supply. Nominally
AJ16,AJ9,AK9,C10,C11,C22,C23,C9,D10,D23,D9, 1.8 volt (Core
E11,E20,E21,E22,J26,J27,J4,J5,K26,K27,K3,K5, voltage).
L26,L27,L3,L5,Y26, Y27,Y3,Y5
A29,A30,AF5,AG15,AG16,AG26,AG27,AG4,AH15 Ground
,
AH16,AH21,AH28,AH3,AJ2,AJ21,AJ29,AK1,AK30,
B1,B15,B16,B2,B29,C15,C16,C28,C3,D15,D16,
D27,D4,E26,E5,N13,N14,N15,N16,N17,N18,P13,
P14,P15,P16,P17,P18,R13,R14,R15,R16,R17,
R18,R2,R27,R28,R29,R3,R4,T13,T14,T15,T16,
T17,T18,T2,T27,T28,T29,T3,T4,U13,U14,U15,
U16,U17,U18,V13,V14,V15,V16, V17,V18
TEST PINS
M4,AK26,M3,AJ4,AK4,AK25,K30,N28
Internal
Connection.
Connected to VSS
for normal
operation.
D8,P28,C12,AK10,AH12,AD29,H28,J29,AC28,
D12,P29,E9,AJ11,AK11,AD30,G28,H29,AB27,A3,
P2,A2,Y1,AA1,AJ17,C20,B21,AK17,B3,P1,D3,
AA2,AB1,AK18,B22,D21,AJ18,C2,R1,E3,AB2,
AB4,AH18,D19,A22,AK19,D2,T1,E4,AC1,AC2,
AG18,A21,B20,AJ19,C1,U1,F4,AC4,AD1,AK20,
C19,A20,AH19,F3,U2,E2,AC3,AD2,AK21,B19,
A19,AG19,E10,P30,B12,AJ12,AG13,AC29,J30,
G29,AC30,A11,N30,D11,AH13,AK12,AB29,H30,
G30,AB30,A10,N27,B11,AJ13,AG14,AA27,F29,
F30,AA29,A9,A14,B10,AG11,AG12,Y28,E29,E28,
AA30,A8,A13,B9,AJ10,AF10,Y29,D29,E30,Y30,
C8,B14,B8,AG9,AH9,W28,D26,D28,W29,C4,
E12,C5,AA4,Y4,R30,A23,B23,
T30,B4,P3,A4,Y2,W1,AG17,D20,C21,AH17
No connection.
These pins must be
left open for normal
operation.
5
Zarlink Semiconductor Inc.
5 Page 
ZL50211
Data Sheet
In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the
DTDT is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The EVP allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
where 0 < DTDT(dec) < 1
DTDT(hex) = hex(DTDT(dec) * 32768)
Example:For DTDT = 0.5625 (-5 dB), the hexadecimal value becomes hex(0.5625 * 32768) = 4800hex
1.3 Path Change Detector
Integrated into the EVP is a Path Change Detector. This permits fast reconvergence when a major change occurs
in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is
achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,
the existing echo channel estimate will also be cleared (i.e., the adaptive filter will be filled with zeroes) upon
detection of a major path change.
1.4 Non-Linear Processor (NLP)
After echo cancellation, there is always a small amount of residual echo which may still be audible. The EVP uses
Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal
as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be
calculated by the following equation:
TSUP = Lrin + 20log10(NLPTHR)
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed
in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the
following equation:
where 0 < NLPTHR(dec) < 1
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal
by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a
spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the
perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted
that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL50211.PDF ] | |
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