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HD74LS165A PDF даташит

Спецификация HD74LS165A изготовлена ​​​​«Renesas Technology» и имеет функцию, называемую «Parallel-Load 8-bit Shift Register».

Детали детали

Номер произв HD74LS165A
Описание Parallel-Load 8-bit Shift Register
Производители Renesas Technology
логотип Renesas Technology логотип 

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HD74LS165A Даташит, Описание, Даташиты
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HD74LS165A
Parallel-Load 8-bit Shift Register
REJ03D0449–0300
Rev.3.00
Jul.15.2005
The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in
access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /
load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs
are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit
function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift /
load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the
clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are
loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the
clock, clock inhibit, or serial inputs.
Features
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS165AP
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74LS165AFPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Pin Arrangement
Shift/
Load
Clock
1
2
E3
F4
Parallel
Inputs G 5
H6
Output QH 7
GND 8
Shift/Load
CK Clock
Inhibit
ED
FC
GB
HA
QH
Serial
QH Input
16 VCC
15
Clock
Inhibit
14 D
13 C
12 B
Parallel
Inputs
11 A
10
Serial
Input
9 Output QH
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 7









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HD74LS165A Даташит, Описание, Даташиты
HD74LS165A
Function Table
Shift / Load
Clock
Inhibit
Inputs
Clock
Serial
Parallel
AH
Internal outputs
QA QB
Output
QH
L X X X ah a b h
H
L
X
X
QA0
QB0
QH0
H
L
H
X
H
QAn
QGn
H
L
L
X
L
QAn
QGn
H
H
X
X
X
QA0
QB0
QH0
Notes: 1. H; high level, L; low level, X; irrelevant
2. ; transition from low to high level
3. a to h; the level of steady-state input at inputs A to H respectively
4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were
established.
5. QAn to QGn; the level of QA to QG, respectively, before the most recent transition of the clock.
Block Diagram
A B C D E FGH
Serial
Input
Shift /
Load
PR
S QA
CK
R QA
Clear
PR
S QB
CK
R QB
Clear
PR
S QC
CK
R QC
Clear
PR
S QD
CK
R QD
Clear
PR
S QE
CK
R QE
Clear
PR
S QF
CK
R QF
Clear
PR
S QG
CK
R QG
Clear
PR
S QH
CK
R QH
Clear
QH
QH
Clock
Clock
Inhibit
Absolute Maximum Ratings
Item
Symbol
Ratings
Supply voltage
VCC
7
Input voltage
VIN 7
Power dissipation
PT 400
Storage temperature
Tstg –65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Unit
V
V
mW
°C
Rev.3.00, Jul.15.2005, page 2 of 7









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HD74LS165A Даташит, Описание, Даташиты
HD74LS165A
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Clock pulse width
Load pulse width
Clock enable setup time
Parallel input setup time
Serial input setup time
Shift setup time
Hold time
Symbol
VCC
IOH
IOL
Topr
ƒclock
tw (clock)
tw (load)
tsu
tsu
tsu
tsu
th
Min
4.75
–20
0
25
15
30
10
20
45
0
Typ
5.00
25
Max
5.25
–400
8
75
25
Unit
V
µA
mA
°C
MHz
ns
ns
ns
ns
ns
ns
ns
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Symbol min. typ.* max. Unit
Condition
Input voltage
VIH 2.0 — — V
VIL — — 0.8 V
Output voltage
VOH 2.7 —
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
VOL
— 0.4
— 0.5
V IOL = 4 mA VCC = 4.75 V, VIH = 2 V,
IOL = 8 mA VIL = 0.8 V
Input current
Shift / Load
Other inputs
II
— — 0.3 mA
— — 0.1 mA VCC = 5.25 V, VI = 7 V
High level
input current
Shift / Load
Other inputs
IIH
— — 60 µA
— — 20 µA VCC = 5.25 V, VI = 2.7 V
Low level input Shift / Load
current
Other inputs
IIL
— — –1.2 mA
–0.4
mA VCC = 5.25 V, VI = 0.4 V
Short-circuit output current
IOS –20 — –100 mA VCC = 5.25 V
Supply current**
ICC — 21 36 mA VCC = 5.25 V
Input clamp voltage
VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Note: * VCC = 5 V, Ta = 25°C
**. With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift / load, ICC is
measured with the parallel inputs at 4.5 V, than with the parallel inputs grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Symbol Inputs Outputs min. typ. max. Unit Condition
Maximum clock frequency
ƒmax
25 35 — MHz
tPLH Load Any — 21 35 ns
tPHL — 26 35 ns
Propagation delay time
tPLH Clock Any
tPHL
14
16
25
25
ns
ns
CL = 15 pF,
RL = 2 k
tPLH
tPHL
H
— 13 25 ns
QH — 24 30 ns
tPLH
tPHL
H
— 19 30 ns
QH — 17 25 ns
Rev.3.00, Jul.15.2005, page 3 of 7










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HD74LS165AParallel-Load 8-bit Shift RegisterRenesas Technology
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