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PDF 74VCX16373 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX16373 | |
| Descripción | Low-Voltage 1.8/2.5/3.3V 16-Bit Transparent Latch | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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74VCX16373
Low−Voltage 1.8/2.5/3.3V
16−Bit Transparent Latch
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74VCX16373 is an advanced performance, non−inverting
16−bit transparent latch. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCX16373 is byte controlled, with each byte functioning identically,
but independently. Each byte has separate Output Enable and Latch
Enable inputs. These control pins can be tied together for full 16−bit
operation.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.
The 74VCX16373 contains 16 D−type latches with 3−state
3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are
HIGH, data on the Dn inputs enters the latches. In this condition, the
latches are transparent, (a latch output will change state each time its
D input changes). When LE is LOW, the latch stores the information
that was present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3−state outputs are controlled
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches.
Features
• Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation:3.0 ns max for 3.0 V to 3.6 V
3.9 ns max for 2.3 V to 2.7 V
6.8 ns max for 1.65 V to 1.95 V
• Static Drive:
±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
±6 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0 V
• Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
• All Devices in Package TSSOP are Inherently Pb−Free*
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
VCX16373
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN NAMES
Pins
Function
OEn
LEn
D0−D15
O0−O15
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
ORDERING INFORMATION
Device
Package
Shipping†
74VCX16373DT
TSSOP
(Pb−Free)
39 / Rail
74VCX16373DTR
TSSOP
(Pb−Free)
2500 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
74VCX16373/D
1 page  
74VCX16373
AC CHARACTERISTICS (Note 4; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V
Symbol
Parameter
Waveform Min Max Min Max
Min
Max
tPLH Propagation Delay
tPHL
Dn−to−On
1
0.8 3.0 1.0 3.4
1.5
0.8 3.0 1.0 3.4
1.5
6.8
6.8
tPLH Propagation Delay
tPHL
LE−to−On
1
0.8 3.0 1.0 3.9
1.5
0.8 3.0 1.0 3.9
1.5
7.8
7.8
tPZH
tPZL
Output Enable Time to
High and Low Level
2
0.8 3.5 1.0 4.6
1.5
0.8 3.5 1.0 4.6
1.5
9.2
9.2
tPHZ Output Disable Time From 2 0.8 3.5 1.0 3.8 1.5
tPLZ High and Low Level
0.8 3.5 1.0 3.8
1.5
6.8
6.8
ts Setup Time, High or Low
Dn−to−LE
3 1.5
1.5
2.5
Unit
ns
ns
ns
ns
ns
th Hold Time, High or Low
Dn−to−LE
3 1.0
1.0
1.0
ns
tw LE Pulse Width, High
3 1.5
1.5
4.0
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 5)
0.5 0.5
0.5 0.5
0.75 ns
0.75
4. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 W)
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
Symbol
Parameter
Waveform
Min
Max Min Max Unit
tPLH Propagation Delay
tPHL
Dn−to−On
4 1.0
1.0
3.6
3.6
4.3 ns
4.3
tPLH Propagation Delay
tPHL
LE−to−On
4 1.0
1.0
3.9
3.9
4.6 ns
4.6
tPZH
tPZL
Output Enable Time to
High and Low Level
5
1.0
1.0
4.7
4.7
5.7 ns
5.7
tPHZ
tPLZ
Output Disable Time From
High and Low Level
5
1.0
1.0
4.1
4.1
4.5 ns
4.5
tOSHL
tOSLH
Output−to−Output Skew
(Note 6)
0.5 0.5 ns
0.5 0.5
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
http://onsemi.com
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| PDF Descargar | [ Datasheet 74VCX16373.PDF ] | |
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