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PDF W83194BR-323 Data sheet ( Hoja de datos )
| Número de pieza | W83194BR-323 | |
| Descripción | STEPLESS CLOCK | |
| Fabricantes | Winbond | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de W83194BR-323 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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W83194BR-323/W83194BG-323
STEPLESS CLOCK FOR INTEL
BROOKDALE CHIPSET
www.DataSheet4U.com
Date: 03/22/2006
Revision: 2.1
1 page  
W83194BR-323W83194BG-323
STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET
3. BLOCK DIAGRAM
PLL2
XIN
XOUT
XTAL
OSC
PLL1
Spread
Spectrum
VTTPWRGD#
FS<4:0>
M/N/Ratio
S.S.P
ROM
Latch
&
POR
PD#
PCI_STOP#
CPU_STOP#
2
MULTISEL 0:1
*SDATA
*SDCLK
Control
Logic
&
Config
Register
I2C
interface
Driver
1/2 Mux
VCOCLK
Divider
/2,/4,/8,/16
/3,/6,/12
/5,/10,/20
/7,/14
/9,/18
Stop
Stop
48MHz
24_48MHz
2
REF0:1
3
CPUCLK_T 0:2
CPUCLK_C 0:2
3
4
3V66_0:3
1
0 PCICLK_F0:2
PCICLK_0:6
RESET#
Rref
4. PIN CONFIGURATION
*MULTSEL1/REF1
VDDREF
Xin
Xout
GND
PCICLK_F0/*FS2
PCICLK_F1/*FS3
PCICLK_F2/&SEL24_4
8 VDDPCI
PCICLK0/*FS4
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDPCI
VTTPWRGD#
RESET#
GND
48MHz/*FS0
24_48MHz/*FS1
VDD48
1
2
3
4
5
6
7
8
89
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
* :internal 120K pull-up
&:internal 120K pull-down
#: active low
48 *MULTSEL0/REF0
47 GND
46 VDDCPU
45 CPUCLK_T2
44 CPUCLK_C2
43 GND
42 *PD#
41 CPUCLK_T0
40 CPUCLK_C0
39 VDDCPU
38 CPUCLK_T1
37 CPUCLK_C1
36 GND
35 IREF
34 VDDCORE
33 GND
32 VDD3V66
31 3V66_0
30 3V66_1
29 GND
28 3V66_2
27 3V66_3 / 48MHz /*SEL48_66
26 *SDCLK
25 *SDATA
-2-
5 Page 
W83194BR-323W83194BG-323
STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET
7.4 Register 3: PCI, 48MHz Clock Register (1 = enable, 0 = Stopped)
BIT PIN NO
7 22
6 23
5 48
41
3 Reserved
28
17
06
PWD
1 48MHZ
1 24_48MHz
1 REF0
1 REF1
1 Reserved
1 PCICLK_F2
1 PCICLK_F1
1 PCICLK_F0
DESCRIPTION
7.5 Register 4: 3V66 Control Register (1 = enable, 0 = Stopped)
BIT PIN NO
7-
6-
5-
4-
3 27
2 28
1 30
0 31
PWD
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 3V66_3 / 48MHz
1 3V66_2
1 3V66_1
1 3V66_0
DESCRIPTION
7.6 Register 5: Watchdog Control Register
BIT
NAME
PWD
DESCRIPTION
7 MULTISEL1
X MULTISEL1 trapping pin data read back
6 EN_WD
0 Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer.
Read this bit will return a counting state. If timer continues down count,
this bit will return 1. Otherwise, this bit will return 0.
5 WD_TIMEOUT 0 Watchdog Timeout Status. If the watchdog is started and timer down
counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1,
when the watchdog is restart in the next time. This bit is Read Only.
4 SAF_FREQ [4] 0
3 SAF_FREQ [3] 0
2
SAF_FREQ [2]
0
Watchdog safe frequency bits. These bits will be reloaded into FS [4:0],
if the watchdog is timeout and enable reload safe frequency bits.
1 SAF_FREQ [1] 0
0 SAF_FREQ [0] 0
-8-
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet W83194BR-323.PDF ] | |
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