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PDF CAT24C128 Data sheet ( Hoja de datos )

Número de pieza CAT24C128
Descripción 128-Kb I2C CMOS Serial EEPROM
Fabricantes Catalyst Semiconductor 
Logotipo Catalyst Semiconductor Logotipo



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No Preview Available ! CAT24C128 Hoja de datos, Descripción, Manual

CAT24C128
128-Kb I2C CMOS Serial EEPROM
FEATURES
Supports Standard and Fast I2C Protocol
1.8V to 5.5V Supply Voltage Range
64-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8-lead PDIP, SOIC and TSSOP
packages
DEVICE DESCRIPTION
The CAT24C128 is a 128-Kb Serial CMOS EEPROM,
internally organized as 256 pages of 64 bytes each, for
a total of 16,384 bytes of 8 bits each.
It features a 64-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory).
For Ordering Information details, see page 14.
www.DataSheet4U.com
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (W)
TSSOP (Y)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2
SDA
SCL
WP
VCC
VSS
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
A2, A1, A0
WP
VCC
CAT24C128
VSS
SDA
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1103, Rev. G

1 page




CAT24C128 pdf
Figure 1. START/STOP Conditions
CAT24C128
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
DEVICE ADDRESS
1 0 1 0 A2 A1 A0 R/W
Figure 3. Acknowledge Timing
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
18
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (tAA)
BUS RELEASE DELAY (RECEIVER)
9
ACK SETUP (tSU:DAT)
Figure 4. Bus Timing
tF
SCL
tSU:STA
SDA IN
SDA OUT
tLOW
tHIGH
tLOW
tR
tHD:DAT
tHD:STA
tSU:DAT
tAA tDH
tSU:STO
tBUF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1103, Rev. G

5 Page





CAT24C128 arduino
8-LEAD 150 MIL WIDE SOIC (W)
CAT24C128
E1
E
D
A
e
b
A1
SYMBOL
A1
A
b
C
D
E
E1
e
h
L
θ1
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
0.25
0.40
0°
NOM
1.27 BSC
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
0.50
1.27
8°
h x 45
θ1
L
C
24C16_8-LEAD_SOIC.eps
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-012.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 1103, Rev. G

11 Page







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