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PDF CAT24C164 Data sheet ( Hoja de datos )
| Número de pieza | CAT24C164 | |
| Descripción | 16-Kb CMOS Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24C164
16-Kb CMOS Serial EEPROM, Cascadable
FEATURES
■ Supports Standard and Fast I2C Protocol
■ 1.8 V to 5.5 V Supply Voltage Range
■ 16-Byte Page Write Buffer
■ Hardware Write Protection for entire memory
■ Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Industrial temperature range
■ RoHS-compliant 8-lead PDIP, SOIC, TSSOP and
8-pad TDFN packages.
DEVICE DESCRIPTION
The CAT24C164 is a 16-Kb CMOS cascadable Serial
EEPROM device organized internally as 128 pages of
16 bytes each, for a total of 2048x8 bits. The device
supports both the Standard (100 kHz) as well as Fast
(400 kHz) I2C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address
up to eight CAT24C164 devices on the same bus.
For Ordering Information details, see page 15.
PIN CONFIGURATION
www.DataSheet4U.com
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (W)
TSSOP (Y)
TDFN (VP2)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2
SDA
SCL
WP
VCC
VSS
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
A2, A1, A0
WP
VCC
CAT24C164
VSS
SDA
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1118, Rev. A
1 page  
Figure 1. START/STOP Conditions
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1 A2 A1 A0 a10 a9 a8 R/W CAT24C164
CAT24C164
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
BUS RELEASE DELAY (RECEIVER)
9
ACK SETUP (≥ tSU:DAT)
Figure 4. Bus Timing
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
tSU:STO
tBUF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1118, Rev. A
5 Page 
8-LEAD 150 MIL WIDE SOIC (W)
CAT24C164
E1
E
D
A
e
b
A1
SYMBOL
A1
A
b
C
D
E
E1
e
h
L
θ1
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
0.25
0.40
0°
NOM
1.27 BSC
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
0.50
1.27
8°
h x 45
θ1
L
C
24C16_8-LEAD_SOIC.eps
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-012 dimensions.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 1118, Rev. A
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CAT24C164.PDF ] | |
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