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PDF CAT24FC64 Data sheet ( Hoja de datos )
| Número de pieza | CAT24FC64 | |
| Descripción | 64K-Bit I2C Serial CMOS EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24FC64
64K-Bit I2C Serial CMOS EEPROM
FEATURES
I Fast mode I2C bus compatible*
I Industrial and extended
temperature ranges
I Max clock frequency:
I 5 ms max write cycle time
- 400KHz for VCC=2.5V to 5.5V
I Schmitt trigger filtered inputs for noise suppression
I Low power CMOS technology
I 64-byte page write buffer
rtI Self-timed write cycle with auto-clear
I Write protect feature
– entire array protected when WP at VIH
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
aThe CAT24FC64 is a 64K-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
PCatalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC64
features a 64-byte page write buffer. The device oper-
ates via the I2C bus serial interface and is available in 8-
pin DIP, SOIC, TSSOP and TDFN packages.
dPIN CONFIGURATION
BLOCK DIAGRAM
eDIP Package (P, L, GL) TDFN Package (RD2, ZD2)
EXTERNAL LOAD
A0
uA1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
tinSOIC Package
(J, W, K, X, GW, GX)
A0 1
A1 2
A2 3
VSS 4
(Top View)
8 VCwCww.DataSheet4U.com
7 WP
6 SCL
5 SDA
VCC
VSS
TSSOP Package (U, Y, GY)
SDA
nA0
A1
oA2
VSS
1
2
3
4
8 VCC A0 1
7 WP A1 2
6 SCL A2
3
5 SDA VSS 4
8 VCC
7 WP
6 SCL
5 SDA WP
DOUT
ACK
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
EEPROM
128 128X512
cPIN FUNCTIONS
isPin Name
Function
A0, A1, A2 Address Inputs
DSDA
Serial Data/Address
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL Serial Clock
WP Write Protect
SCL
STATE COUNTERS
VCC +2.5V to +5.5V Power Supply
VSS Ground
A0 SLAVE
A1 ADDRESS
A2 COMPARATORS
NC No Connect
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1046, Rev. K
1 page  
CAT24FC64
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as as many as eight devices on the same bus. These bits
follows:
must compare to their hardwired input pins. The last bit
(1) Data transfer may be initiated only when the bus is
not busy.
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
(2) During a data transfer, the data line must remain
operation is selected.
stable whenever the clock line is high. Any changes After the Master sends a START condition and the slave
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
rtdevice, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC64 monitors the
SDA and SCL lines and will not respond until this
condition is met.
aSTOP Condition
PA LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
dDEVICE ADDRESSING
eThe bus Master begins a transmission by sending a
START condition. The Master sends the address of the
uparticular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC64 uses the next three bits
tinas address bits. The address bits A2, A1 and A0 allow
address byte, the CAT24FC64 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC64 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24FC64 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24FC64 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24FC64 will continue to transmit
Figure 4. Acknowledge Timing
nSCL FROM
oMASTER
1
89
cDATA OUTPUT
FROM TRANSMITTER
isDATA OUTPUT
D FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1046, Rev. K
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT24FC64.PDF ] | |
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