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CAT24FC66 PDF даташит

Спецификация CAT24FC66 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «(CAT24FC65 / CAT24FC66) 64K-Bit I2C Serial CMOS EEPROM».

Детали детали

Номер произв CAT24FC66
Описание (CAT24FC65 / CAT24FC66) 64K-Bit I2C Serial CMOS EEPROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT24FC66 Даташит, Описание, Даташиты
CAT24FC65, CAT24FC66
64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection
FEATURES
I Fast mode I2C bus compatible*
I Max clock frequency:
- 400KHz for VCC=2.5V to 5.5V
I Schmitt trigger filtered inputs for
noise suppression
I Low power CMOS technology
I 64-byte page write buffer
I Self-timed write cycle with auto-clear
I Industrial and automotive temperature ranges
I 5 ms max write cycle time
I Write protect feature
– Bottom 1/4 array protected when WP at V
IH
(CAT24FC65)
– Top 1/4 array protected when WP at VIH
(CAT24FC66)
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
The CAT24FC65/66 is a 64k-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements.
The CAT24FC65/66 features a 64-byte page write
buffer. The device operates via the I2C bus serial
interface and is available in 8-pin DIP, SOIC, TSSOP
and TDFN packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package
(J, W, K, X, GW, GX)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
TDFN Package (RD2, ZD2)
EXTERNAL LOAD
www.DataSheet4U.com
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
TSSOP Package (U, Y, GY)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
Pin Name
Function
A0, A1, A2 Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +2.5V to +5.5V Power Supply
VSS Ground
NC No Connect
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
EEPROM
128 128X512
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1047, Rev. H









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CAT24FC66 Даташит, Описание, Даташиты
CAT24FC65/66
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55°C to +125°C
Storage Temperature ....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... 2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... 2.0V to +7.0V
RELIABILITY CHARACTERISTICS (3)
Symbol
Parameter
NEND
Endurance
TDR Data Retention
VZAP
ILTH(4)
ESD Susceptibility
Latch-up
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
*COMMENT
Stresses above those listed under Absolute Maximum Ratingsmay
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Min
1,000,000
100
4000
100
Typ
Max Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +5.5V, unless otherwise specified.
Symbol Parameter
Test Conditions Min Typ Max Units
ICC1 Power Supply Current - Read
fSCL = 400 KHz
VCC=5V
400 µA
ICC2 Power Supply Current - Write
ISB(5) Standby Current
ILI Input Leakage Current
ILO Output Leakage Current
fSCL = 400KHz
VCC=5V
VIN = GND or VCC
VCC=5V
VIN = GND to VCC
VOUT = GND to VCC
3 mA
1 µA
1 µA
1 µA
VIL Input Low Voltage
-0.5 VCC x 0.3 V
VIH Input High Voltage
VCC x 0.7
VCC + 0.5 V
VOL1 Output Low Voltage (VCC = +3.0V)
IOL = 3.0 mA
0.4 V
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test
Conditions
CI/O(3) Input/Output Capacitance (SDA)
VI/O = 0V
CIN(3)
Input Capacitance (SCL, WP, A0, A1)
VIN = 0V
ZWPL
WP Input Impedance
VIN 0.5V
ZWPH
WP Input Impedance
VIN>0.7VxVCC
Min
5
500
Typ
Max Units
8 pF
6 pF
70 k
k
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
(5) Standby current (ISB ) = 10 µA max at extended temperature range.
Doc. No. 1047, Rev. H
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice









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CAT24FC66 Даташит, Описание, Даташиты
CAT24FC65/66
A.C. CHARACTERISTICS
VCC = +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
FSCL
tAA
t (2)
BUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
t
SU:DAT
t (2)
R
t (2)
F
tSU:STO
tDH
tWR
tSP
tSU;WP
tHD;WP
Clock Frequency
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission
Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppresssion (SDA, SCL)
WP Setup Time
WP Hold Time
VCC=2.5V - 5.5V
Min Max
400
50 900
1300
600
1300
600
600
0
100
600
50
600
1300
300
300
5
50
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
Power-Up Timing (2)(3)
Symbol Parameter
Min Typ Max Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1 ms
1 ms
Note:
(1) AC measurement conditions:
RL (connects to VCC): 0.3VCC to 0.7 VCC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 VCC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1047, Rev. H










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