|
|
PDF CAT24WC66 Data sheet ( Hoja de datos )
| Número de pieza | CAT24WC66 | |
| Descripción | 64K-bit I2C Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CAT24WC66 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
CAT24WC66
64K-bit I2C Serial EEPROM with Partial Array Write Protection
FEATURES
400kHz I2C Bus
1.8V to 5.5V supply voltage range
Cascadable for up to eight devices
32-byte page write buffer
Self-timed write cycle with auto-clear
Schmitt trigger inputs for noise protection
Write protection
— Top 1/4 array protected when WP at VIH
1,000,000 program/erase cycles
100 year data retention
Industrial and automotive temperature ranges
RoHS-compliant packages
DESCRIPTION
The CAT24WC66 is a 64K-bit Serial CMOS EEPROM
internally organized as 8192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24WC66
features a 32-byte page write buffer. The device
operates via the I2C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
For Ordering Information details, see page 12.
PIN CONFIGURATION
www.DataSheet4U.com
FUNCTIONAL SYMBOL
DIP Package (L)
SOIC Package (W, X)
A0
A1
A2
VSS
1
2
3
4
8 VCC
A0 1
7 WP
A1 2
6 SCL
A2 3
5 SDA VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SCL
A2, A1, A0
VCC
CAT24CW66
PIN FUNCTION
WP
Pin Name
A0, A1, A2
SDA
SCL
WP
VCC
VSS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
Power Supply
Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I2C Bus Protocol.
VSS
SDA
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1037 Rev. J
1 page  
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC66 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 1010 (Fig. 5). The next three bits (A2, A1,
A0) are the device address bits; up to eight 64K
devices may to be connected to the same bus. These
bits must compare to the hardwired input pins, A2, A1
and A0. The last bit of the slave address specifies
CAT24WC66
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the
slave address byte, the CAT24WC66 monitors the
bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
address. The CAT24WC66 then performs a Read or
Write operation depending on the state of the R/¯W¯ bit.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
The CAT24WC66 responds with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with a
write operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT24WC66 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC66 will continue to
transmit data. If no acknowledge is sent by the
Master, the device terminates data transmission and
waits for a STOP condition. The master must then
issue a stop condition to return the CAT24WC66 to
the standby power mode and place the device in a
known state.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Slave Address Bits
ACKNOWLEDGE
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1 0 1 0 A2 A1 A0 R/W
DEVICE ADDRESS
5
Doc. No. 1037 Rev. J
5 Page 
8-LEAD 208 MIL SOIC (X)
CAT24WC66
E
b
D
e
A
A1
Ө1
SYMBOL
A1
A
b
c
D
E
E1
e
L
Ө1
MIN
0.05
0.36
0.19
5.13
7.75
5.13
0.51
0°
NOM
1.27 BSC
MAX
0.25
2.03
0.48
0.25
5.33
8.26
5.33
0.76
8°
L
c
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1.Compliant with EIAJ specification EDR-7320
2. All dimensions in millimeters
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1037 Rev. J
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CAT24WC66.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CAT24WC64 | 32K/64K-Bit I2C Serial CMOS E2PROM | Catalyst Semiconductor |
| CAT24WC64 | (CAT24WC32 / CAT24WC64) 32K / 64K-Bit IC Serial CMOS EEPROM | Catalyst Semiconductor |
| CAT24WC65 | 32K/64K-Bit I2C Serial CMOS E2PROM | Catalyst Semiconductor |
| CAT24WC66 | 64K-bit I2C Serial EEPROM | Catalyst Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |