CAT1022 Datasheet PDF - Catalyst Semiconductor
| Part Number | CAT1022 | |
| Description | (CAT1021 - CAT1023) Supervisory Circuits | |
| Manufacturers | Catalyst Semiconductor | |
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There is a preview and CAT1022 download ( pdf file ) link at the bottom of this page. Total 21 Pages | ||
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CAT1021, CAT1022, CAT1023
Supervisory Circuits with I2C Serial 2k-bit CMOS
EEPROM, Manual Reset and Watchdog Timer
FEATURES
DESCRIPTION
Precision Power Supply Voltage Monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
Watchdog Timer
Active High or Low Reset
The CAT1021, CAT1022 and CAT1023 are complete
memory and supervisory solutions for microcontroller-
based systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection are
integrated together in low power CMOS technology.
Memory interface is via a 400kHz I2C bus.
— Valid reset guaranteed at VCC = 1V
400kHz I2C Bus
2.7V to 5.5V Operation
Low power CMOS technology
The CAT1021 and CAT1023 provide a precision VCC
sense circuit and two open drain outputs: one (RESET)
drives high and the other (R¯¯E¯S¯E¯T¯) drives low whenever
VCC falls below the reset threshold voltage. The
CAT1022 has only a R¯¯E¯S¯E¯T¯ output and does not have
16-Byte Page Write Buffer
Built-in inadvertent write protection
a Write Protect input. The CAT1021 also has a Write
Protect input (WP). Write operations are disabled if WP
is connected to a logic high.
— WP pin (CAT1021)
1,000,000 Program/Erase cycles
Manual Reset Input
All supervisors have a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. For the
100 year data retention
CAT1021www.DataSheet4U.com and CAT1022, the watchdog timer monitors
the SDA signal. The CAT1023 has a separate watchdog
Industrial and extended temperature ranges
timer interrupt input pin, WDI.
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3 mm foot-print) packages
— TDFN max height is 0.8mm
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply voltage
exceeds the reset threshold level. With both active high
and low reset signals, interface to microcontrollers and
other ICs is simple. In addition, the R¯¯E¯S¯E¯T¯ pin or a
separate input, ¯M¯R¯, can be used as an input for push-
For Ordering Information details, see page 19.
button manual reset capability.
The on-chip, 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided
by a VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until VCC
reaches the reset threshold during power up.
Available packages include an 8-pin DIP and surface
mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin
MSOP packages. The TDFN package thickness is
0.8mm maximum. TDFN footprint options are 3x3mm.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 3009 Rev. L
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CAT1021, CAT1022, CAT1023
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
COUT(1)
CIN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
VOUT = 0V
VIN = 0V
Max
8
6
Units
pF
pF
AC CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol Parameter
Min Max Units
fSCL Clock Frequency
tSP Input Filter Spike Suppression (SDA, SCL)
400 kHz
100 ns
tLOW Clock Low Period
1.3 µs
tHIGH
tR(1)
tF(1)
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
0.6
300
300
µs
ns
ns
tHD; STA
tSU; STA
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
0.6 µs
0.6 µs
tHD; DAT Data Input Hold Time
0 ns
tSU; DAT Data Input Setup Time
100 ns
tSU; STO Stop Condition Setup Time
0.6 µs
tAA SCL Low to Data Out Valid
900 ns
tDH Data Out Hold Time
50 ns
tBUF(1) Time the Bus must be Free Before a New Transmission Can Start
1.3
µs
tWC(3) Write Cycle Time (Byte or Page)
5 ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 3009 Rev. L
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CAT1022 electronic component. |
| Information | Total 21 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CAT1022.PDF Datasheet ] | |
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