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CAT24WC164 PDF даташит

Спецификация CAT24WC164 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «16K-Bit Serial EEPROM».

Детали детали

Номер произв CAT24WC164
Описание 16K-Bit Serial EEPROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT24WC164 Даташит, Описание, Даташиты
CAT24WC164
ALOGEN FR
16K-Bit Serial EEPROM, Cascadable
LEA D F REETM
FEATURES
I Self-timed write cycle with auto-clear
I 400 kHz I2C bus compatible*
I 1,000,000 program/erase cycles
I 1.8 to 5.5 volt operation
I 100 year data retention
I Low power CMOS technology
I Write protect feature
- Entire array protected when WP at V
IH
I Page write buffer
rtDESCRIPTION
aThe CAT24WC164 is a16K-bit, cascadable Serial CMOS
EEPROM internally organized as 2048 words of 8 bits
each. Catalyst’s advanced CMOS technology substan-
Ptially reduces device power requirements. The
I 8-pin DIP, 8-pin SOIC, 8-pin MSOP or
8 pin TSSOP
(Also available in "Green" packages)
I Industrial, automotive and
extended temperature ranges
CAT24WC164 features a 16-byte page write buffer. The
device operates via the I2C bus serial interface, has a
special write protection feature, and is available in 8-pin
DIP, 8-pin SOIC, 8-pin TSSOP and 8-lead MSOP.
dPIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L)
SOIC Package (J, W)
EXTERNAL LOAD
eA0
A1
uA2
tinVSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WPwww.DataSheet4U.com
6 SCL
5 SDA
VCC
5020 FHD F01
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
MSOP Package (R, Z)
TSSOP Package (U, Y)
nA0
A1
oA2
VSS
1
2
3
4
8 VCC
A0
7 TEST A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8
7
6
5
SDA
VCC
WP
SCL
SDA WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
iscPIN FUNCTIONS
Pin Name
Function
DA0, A1, A2 Device Address Inputs
DATA IN STORAGE
SDA
Serial Data/Address
HIGH VOLTAGE/
TIMING CONTROL
SCL Serial Clock
WP Write Protect
SCL STATE COUNTERS
VCC +1.8V to +5.5V Power Supply
VSS Ground
A0 SLAVE
A1 ADDRESS
A2 COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1026, Rev. J









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CAT24WC164 Даташит, Описание, Даташиты
CAT24WC164
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. 55°C to +125°C Stresses above those listed under Absolute Maximum
Storage Temperature ....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... 2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... 2.0V to +7.0V
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
Package Power Dissipation
extended periods may affect device performance and
Capability (Ta = 25°C) ................................... 1.0W reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
rtSymbol
Parameter
NEND(3)
aTDR(3)
VZAP(3)
PILTH(3)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
dD.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
eSymbol Parameter
Test Conditions Min Typ Max Units
uICC
ISB(5)
Power Supply Current
Standby Current (VCC = 5.0V)
fSCL = 100 kHz
VIN = GND or VCC
3 mA
1 µA
tinILI Input Leakage Current
VIN = GND to VCC
10 µA
ILO Output Leakage Current
VOUT = GND to VCC
10 µA
VIL Input Low Voltage
1 VCC x 0.3 V
nVIH Input High Voltage
VCC x 0.7
VCC + 0.5 V
oVOL1 Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
0.4 V
VOL2 Output Low Voltage (VCC = 1.8V)
IOL = 1.5 mA
0.5 V
cCAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
isSymbol Parameter
Test Conditions
CI/O(3) Input/Output Capacitance (SDA)
VI/O = 0V
DCIN(3) Input Capacitance
VIN = 0V
Min
Typ Max Units
8 pF
6 pF
(A0, A1, A2, SCL, WP)
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1026, Rev. J
2









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CAT24WC164 Даташит, Описание, Даташиты
CAT24WC164
A.C. CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 5.5 V
2.5 V - 5.5 V
Min Max Min Max
Units
FSCL
TI(1)
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
100
200
tAA SCL Low to SDA Data Out
and ACK Out
3.5
tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
tHD:STA
Start Condition Hold Time
4
0.6
tLOW
tHIGH
tSU:STA
dtHD:DAT
etSU:DAT
tR(1)
utF(1)
tintSU:STO
tDH
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Power-Up Timing(1)(2)
nSymbol
Parameter
tPUR
otPUW
Power-up to Read Operation
Power-up to Write Operation
cWrite Cycle Limits
isSymbol
Parameter
DtWR Write Cycle Time
4.7 1.2
4 0.6
4.7 0.6
00
50 50
1
300
4 0.6
100 100
Min Typ
Min Typ
400 kHz
Part200 ns
1 µs
µs
µs
µs
µs
µs
ns
ns
0.3 µs
300 ns
µs
ns
Max
1
1
Units
ms
ms
Max
5
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3 Doc. No. 1026, Rev. J










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