PDF CAT25C65 Data sheet ( Hoja de datos )

Número de pieza	CAT25C65
Descripción	(CAT25C33 / CAT25C65) 32K/64K-Bit SPI Serial CMOS EEPROM
Fabricantes	Catalyst Semiconductor
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No Preview Available ! CAT25C33/65 32K/64K-Bit SPI Serial CMOS EEPROM FEATURES s 10 MHz SPI compatible s 1,000,000 program/erase cycles s 1.8 to 6.0 volt operation s 100 year data tetention s Hardware and software protection s Low power CMOS technology s SPI modes (0,0 &1,1) s Commercial, industrial, automotive and extended rtstemperature ranges s Self-timed write cycle s 8-pin DIP/SOIC and 14-pin TSSOP s 64-byte page write buffer s Block write protection – Protect first page, last page, any 1/4 or lower 1/2 of EEPROM array DESCRIPTION aThe CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS EEPROM internally organized as 4Kx8/8Kx8 bits. Catalyst’s advanced CMOS Technology substantially Preduces device power requirements. The CAT25C33/ 65 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled dthough a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C32/64 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages. ePIN CONFIGURATION www.DataSheet4U.com SOIC Package (S, V, GV) TSSOP Package (U14, Y14) BLOCK DIAGRAM uCS SO tinWP VSS 1 2 3 4 8 VCC 7 HOLD 6 SCK 5 SI DIP Package (P, L, GL) CS 1 SO 2 NC 3 NC 4 NC 5 WP 6 VSS 7 14 VCC 13 HOLD 12 NC 11 NC 10 NC 9 SCK 8 SI WORD ADDRESS BUFFERS SENSE AMPS SHIFT REGISTERS COLUMN DECODERS nCS SO WP oVSS 1 2 3 4 8 VCC 7 HOLD 6 SCK 5 SI cPIN FUNCTIONS Pin Name Function isSO Serial Data Output SCK Serial Clock DWP Write Protect SO SI CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC XDEC E2PROM ARRAY DATA IN STORAGE HIGH VOLTAGE/ VCC +1.8V to +6.0V Power Supply STATUS TIMING CONTROL VSS Ground REGISTER CS Chip Select SI HOLD Serial Data Input Suspends Serial Input NC No Connect © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1000, Rev. H 1 page CAT25C33/65 SCK: Serial Clock WP: Write Protect SCK is the serial clock pin. This pin is used to synchro- WP is the Write Protect pin. The Write Protect pin will allow nize the communication between the microcontroller normal read/write operations when held high. When WP is and the 25C33/65. Opcodes, byte addresses, or data tied low and the WPEN bit in the status register is set to “1”, present on the SI pin are latched on the rising edge of the all write operations to the status register are inhibited. WP SCK. Data on the SO pin is updated on the falling edge going low while CS is still low will interrupt a write to the status of the SCK. register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the CS: Chip Select WPEN bit is set to 0. CS is the Chip select pin. CS low enables the CAT25C33/ HOLD: Hold 65 and CS high disables the CAT25C33/65. CS high The HOLD pin is used to pause transmission to the takes the SO output pin to high impedance and forces CAT25C33/65 while in the middle of a serial sequence rtsthe devices into a Standby Mode (unless an internal without having to re-transmit entire sequence at a later time. write operation is underway). The CAT25C33/65 draws To pause, HOLD must be brought low while SCK is low. The ZERO current in the Standby mode. A high to low SO pin is in a high impedance state during transition on CS is required prior to any sequence being the time the part is paused, and transitions on the SI pins initiated. A low to high transition on CS after a valid write will be ignored. To resume communication, HOLD is brought asequence is what initiates an internal write cycle. high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high STATUS REGISTER P7 WPEN 6 X 543210 X BP2 BP1 BP0 WEL RDY dMEMORY PROTECTION eBP2 BP1 BP0 u0 0 0 001 tin0 1 0 011 100 n1 0 1 o1 1 0 111 Non-Protection Q1 Protected Q2 Protected Q3 Protected Q4 Protected H1 Protected P0 Protected Pn Protected cWRITE PROTECT ENABLE OPERATION DisWPEN WP WEL MEMORY PROTECTION CAT25C33 Q1 0000-03FF Q2 0400-07FF Q3 0800-0BFF Q4 0C00-0FFF H1 0000-07FF P0 0000-003F Pn 0FC0-0FFF CAT25C65 0000-07FF 0800-0FFF 1000-17FF 1800-1FFF 0000-0FFF 0000-003F 0FC0-1FFF Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1000, Rev. H 5 Page REVISION HISTORY Date Rev. Reason 8/5/2004 F Updated Features Updated DC Operating Characteristics table & notes 07/11/2005 G Update Reliability Characteristic Update Ordering Information 09/22/2005 H Update Pin Configuration PartsCopyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: dDPP ™ AE2 ™ MiniPot™ eCatalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. uCATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING tinOUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. nCatalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate Discotypical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com Publication #: 1000 Revison: H Issue date: 09/22/05 11 Page

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