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ZL50074 PDF даташит

Спецификация ZL50074 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «32 K x 32 K Channel TDM Switch».

Детали детали

Номер произв ZL50074
Описание 32 K x 32 K Channel TDM Switch
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

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ZL50074 Даташит, Описание, Даташиты
ZL50074
32 K x 32 K Channel TDM Switch
with 128 Input and 128 Output Streams
Data Sheet
Features
January 2006
• 32,768 channel x 32,768 channel non-blocking
digital Time Division Multiplex (TDM) switch at
65.536 Mbps, 32.768 Mbps or 16.384 Mbps
• 16,384 channel x 16,384 channel non-blocking
digital TDM switch at 8.192 Mbps
• Up to 128 serial TDM input streams, divided into
32 groups with 4 input streams per group
• Up to 128 serial TDM output streams, divided into
32 groups with 4 output streams per group
• Per-group input bit delay for flexible sampling
point selection
• Per-group output fractional bit advancement
• Four sets of output timing signals for interfacing
additional devices
• Per-channel constant or variable throughput
delay for frame integrity and low latency
applications
Ordering Information
ZL50074GAC 484 Ball LBGA Trays
ZL50074GAG2 484 Ball PBGA** Trays
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Control interface compatible with Intel and
Motorola Selectable 32 bit and 16 bit non-
multiplexed buses
• Connection Memory block programming
• Supports ST-BUS and GCI-Bus standards for
input and output timing
• IEEE 1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core
Applications
• Per-channel high impedance output control
• Large Switching Platforms
• Per-channel force-high output control
• Per-channel message mode
• Centralwww.DataSheet4U.com Office Switches
• Wireless Base Stations and Controllers
• Multi-service Access Platforms
STiA0
STiB0
STiC0
STiD0
:
:
STiA31
STiB31
STiC31
STiD31
FPi2-0
CKi2-0
CK_SEL1-0
FPo3-0
CKo3-0
VDD_CORE VDD_IO VSS
ODE PWR
S/P
Converter
Input
Timing
Data Memory
P/S
Converter
Connection Memory
Output
Timing
Timing
Microprocessor Interface
and Control Registers
Test Access
Port
SToA0
SToB0
SToC0
SToD0
:
:
SToA31
SToB31
SToC31
SToD31
Figure 1 - ZL50074 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.









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ZL50074 Даташит, Описание, Даташиты
ZL50074
Data Sheet
• Digital Loop Carriers
• Time Division Multiplexers
• Media Gateways
Description
The ZL50074 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The
device can switch 64 kbps or Nx64 kbps TDM channels from any input stream to any output stream.
All TDM input and output streams operate at the same rate, either 65.536 Mbps, 32.768 Mbps, 16.384 Mbps or
8.192 Mbps, programmed by the Global Rate Control Register. In 65 Mbps mode, only STiA and SToA streams are
used, resulting in 32 input and 32 output streams. In 32 Mbps mode, STiA, SToA, STiB, and SToB streams are
available, resulting in 64 input and 64 output streams. In 16 Mbps or 8 Mbps mode, STiA, SToA, STiB, SToB, STiC,
SToC, STiD and SToD streams are all available, resulting in 128 input and 128 output streams. The full 32 K x 32 K
channel switching capacity is maintained at bit rates of 65 Mbps, 32 Mbps and 16 Mbps. The capacity reduces to
16 K x 16 K when operating at 8 Mbps.
The ZL50074 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary
and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams
can independently reference their timings to one of the input clocks or to the internal system clock.
The ZL50074 has a variety of user configurable options designed to provide flexibility when data streams are
connected to multiple TDM components or circuits. These include:
• Two additional programmable reference inputs, CKi2 - 1 and FPi2 - 1, which can be used to provide
alternative sources for input and output stream timing
• Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams
connected through different data paths
• Four timing outputs, CKo3 - 0 and FPo3 - 0, which can be configured independently to provide a variety of
clock and frame pulse options
• Support of both ST-BUS and GCI-Bus formats
• Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity
applications
The device contains two types of internal memory: Data Memory and Connection Memory. Incoming TDM data is
stored in the Data Memory. TDM Data is read from the Data Memory controlled by the Connection Memory, and
output on the TDM Output Streams.
There are two major modes of operation: Connection Mode and Message Mode. In Connection Mode, the contents
of the Connection Memory define, for each output stream and channel, the input source stream and channel. In
Message Mode, the Connection Memory is used for the storage of microprocessor data. Using Zarlink's Message
Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This
feature is useful for transferring control and status information for external circuits or other TDM devices.
The non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and
configuration registers used to program ZL50074 options. The port is configurable to interface with either Motorola
or Intel-type microprocessors and is selectable to be either 32 bit or 16 bit.
The mandatory requirements of IEEE 1149.1 (JTAG) standard are supported via the dedicated Test Access Port.
2
Zarlink Semiconductor Inc.









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ZL50074 Даташит, Описание, Даташиты
ZL50074
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3 Stream Provisioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 Output Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Fractional Bit Advancement on Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.0 Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Data Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2 32 Bit Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.3 16 Bit Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.4 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.4.1 Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.4.2 Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.0 Power-up and Initialization of the ZL50074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.1 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.2 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.0 IEEE 1149.1 Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.4 Boundary Scan Description Language (BSDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.0 Memory Map of ZL50074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.0 Detailed Memory and Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.1 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.1.1 Connection Memory Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.1.2 Connection Memory LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.3 Group Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12.4 Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.5 Output Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.6 Block Init Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.7 Block Init Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.8 Global Rate Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.0 DC/AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3
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