NB6N239S PDF даташит
Спецификация NB6N239S изготовлена «ON Semiconductor» и имеет функцию, называемую «3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT Clock Divider». |
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Детали детали
Номер произв | NB6N239S |
Описание | 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT Clock Divider |
Производители | ON Semiconductor |
логотип |
12 Pages
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NB6N239S
3.3 V, 3.0 GHz Any
Differential Clock IN to
LVDS OUT ÷1/2/4/8, ÷2/4/8/16
Clock Divider
Description
The NB6N239S is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive LVDS compatible outputs.
(More device information on page 7). The NB6N239S is a member
of the ECLinPS MAX™ family of high performance clock products.
Features
• Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with B1)
• Input Compatibility with LVDS/LVPECL/CML/HSTL/HCSL
• Rise/Fall Time 120 ps Typical
• < 5 ps Typical Within Device Output Skew
• Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
• Internal 50 W Termination Provided
• Random Clock Jitter < 2 ps RMS
• QA B1 Edge Aligned to QB Bn Edge
• Operating Range: VCC = 3.0 V to 3.465 V with GND = 0 V
• Master Reset for Synchronization of Multiple Chips
• VBBAC Reference Output
• Synchronous Output Enable/Disable
• TIA/EIA − 644 Compliant
• These Devices are Pb−Free and are RoHS Compliant
SELA0
SELA1
CLK
VT
CLK
VBBAC
50 W
50 W
EN
SELB0
SELB1
MR
+
B1
A
B2
B4
B8
R
B2
B4
B B8
B16
Figure 1. Simplified Logic Diagram
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1
Bottom View
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB6N
239S
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
QA
QA
QB
QB
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 6
1
Publication Order Number:
NB6N239S/D
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NB6N239S
MR SELA0 SELA1 VCC
16 15 14 13
VT 1
12 QA
CLK 2
CLK 3
NB6N239S
11 QA
10 QB
VBBAC 4
9 QB
5678
EN SELB0 SELB1 GND
Exposed Pad (EP)
Figure 2. Pinout: QFN−16 (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
1 VT
2 CLK LVDS, LVPECL, CML,
HCSL, HSTL Input
3 CLK LVDS, LVPECL, CML,
HCSL, HSTL Input
4 VBBAC
5 EN* LVCMOS/LVTTL Input
6 SELB0* LVCMOS/LVTTL Input
7 SELB1* LVCMOS/LVTTL Input
8 GND
Power Supply
9 QB
LVDS Output
10 QB
LVDS Output
11 QA
12 QA
LVDS Output
LVDS Output
13 VCC
Power Supply
14 SELA1* LVCMOS/LVTTL Input
15 SELA0* LVCMOS/LVTTL Input
16 MR** LVCMOS/LVTTL Input
EP Power Supply (OPT)
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
Description
Internal 100 W Center−Tapped Termination Pin for CLK and CLK.
Noninverted Differential CLOCK Input.
Inverted Differential CLOCK Input.
Output Voltage Reference for Capacitor Coupled Inputs, only.
Synchronous Output Enable
Clock Divide Select Pin
Clock Divide Select Pin
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 100 W across differential outputs.
Noninverted Differential Output. Typically terminated with 100 W across differential
outputs.
Inverted Differential Output. Typically terminated with 100 W across differential outputs.
Noninverted Differential Output. Typically terminated with 100 W across differential out-
puts.
Positive Supply Voltage.
Clock Divide Select Pin
Clock Divide Select Pin
Master Reset Asynchronous, Default Open High, Asserted LOW
The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The pad is electrically connected to the die, and
is recommended to be electrically and thermally connected to GND on the PC board.
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NB6N239S
SELA0
SELA1
CLK
VT
CLK
50 W
50 W
B1
A B2
B4
R B8
EN
SELB0
R B2
B4
B B8
B16
SELB1
MR
+
VBBAC
Figure 3. Logic Diagram
Table 2. FUNCTION TABLE
CLK EN* MR**
FUNCTION
LH
HH
XXL
Divide
Hold Q
Reset Q
Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS
SELA1* SELA0*
QA Outputs
LL
LH
HL
HH
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS
SELB1* SELB0*
QB Outputs
LL
LH
HL
HH
Divide by 2
Divide by 4
Divide by 8
Divide by 16
= Low−to−High Transition
= High−to−Low Transition
X = Don’t Care
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
+
VCC
QA
QA
QB
QB
GND
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NB6N239S | 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT Clock Divider | ON Semiconductor |
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