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PDF NB7L111M Data sheet ( Hoja de datos )
| Número de pieza | NB7L111M | |
| Descripción | 6.125Gb/s 1:10 Differential Clock/Data Driver | |
| Fabricantes | ON Semiconductor | |
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NB7L111M
2.5V / 3.3V, 6.125Gb/s 1:10
Differential Clock/Data
Driver with CML Output
Description
The NB7L111M is a low skew 1–to–10 differential clock/data
driver, designed with clock/data distribution in mind. It accepts two
clock/data sources into multiplexer input and reproduces ten identical
CML differential outputs. This device is ideal for clock/data
distribution across the backplane or a board, and redundant clock
switchover applications.
The input signals can be either differential or single–ended (if the
external reference voltage is provided). Differential inputs incorporate
internal 50 W termination resistors and accept Negative ECL (NECL),
Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using
appropriate power supplies). The differential 16 mA CML output
provides matching internal 50 W termination, and 400 mV output
swing when externally terminated 50 W to VCC.
The NB7L111M operates from a 2.5 V $5% supply or a
3.3 V $5% supply and is guaranteed over the full industrial
temperature range of −40°C to +85°C. This device is packaged in a
low profile 8x8 mm, QFN−52 package with 0.5 mm pitch (see
package dimension on the back of the datasheet).
Application notes, models, and support documentatiownwwa.rDeataaShveaeti4lUa.cbomle
at www.onsemi.com.
Features
• Maximum Input Clock Frequency > 5.5 GHz Typical
• Maximum Input Data Rate > 6.125 Gb/s Typical
• < 0.5 ps Maximum Clock RMS Jitter
• < 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s
• 50 ps Typical Rise and Fall Times
• 240 ps Typical Propagation Delay
• 2 ps Typical Duty Cycle Skew
• 10 ps Typical Within Device Skew
• 15 ps Typical Device−to−Device Skew
• Operating Range: VCC = 2.5 V $5 and 3.3 V $5
• 400 mV Differential CML Output Swing
• 50 W Internal Input and Output Termination Resistors
• Pb−Free Packages are Available*
http://onsemi.com
1 52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB7L
111M
AWLYYWWG
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 1
1
Publication Order Number:
NB7L111M/D
1 page  
NB7L111M
Table 5. DC CHARACTERISTICS VCC = 2.375 V 2.625 V and 3.135 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C (Notes 6 and 7)
Symbol
Characteristic
Min Typ Max Unit
ICC Power Supply Current (Inputs and Outputs Open)
VCC = 2.375 V to 2.625 V
VCC = 3.135 V to 3.465 V
VOH Output HIGH Voltage (Notes 6 and 7)
VOL Output LOW Voltage (Notes 6 and 7)
VCC = 2.375 V to 2.625 V
VCC = 3.135 V to 3.465 V
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (See Figures 13 and 15)
255
270
VCC − 40
290
305
VCC − 20
325
340
VCC
VCC − 440
VCC − 490
VCC − 350
VCC − 400
VCC – 290
VCC − 340
mA
mV
mV
Vth Input Threshold Reference Voltage Range (Note 8)
VIH Single−ended Input HIGH Voltage (Note 7)
VIL Single−ended Input LOW Voltage (Note 7)
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 14 and 16)
1125
Vth + 75
VEE
VCC – 75
VCC
VCC – 150
mV
mV
mV
VIHD
VILD
VCMR
VID
IIH
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration) (Note 9)
Differential Input Voltage (VIHD − VILD)
Input HIGH Current
(Termination Pins Open)
CLK[0−1]/CLK[0−1]
SEL/SEL
1200
VEE
1163
75
−100
−150
VCC
VCC – 75
VCC – 37
2500
mV
mV
mV
mV
5 100 mA
150
IIL Input LOW Current
(Termination Pins Open)
CLK[0−1]/CLK[0−1]
SEL/SEL
−100
−150
5
100 mA
150
RTIN
RTOUT
RTemp
Coef
Internal Input Termination Resistor
Internal Output Termination Resistor
Internal I/O Termination Resistor Temperature Coefficient
45 50 55 W
45 50 55 W
−3.75
mW/C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. CML outputs require 50 W receiver termination resistors to VCC for proper operation.
7. Input and output parameters vary 1:1 with VCC.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VCMR(MIN) varies 1:1 with VEE, VCMR(MAX) varies 1:1 with VCC.
http://onsemi.com
5
5 Page 
NB7L111M
Application Information
All NB7L111M inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
VCC
minimum input swing of 100 mV and the maximum input
swing of 450 mV. Within these conditions, the input voltage
can range from VCC to 1.2 V. Examples interfaces are
illustrated below in a 50 W environment (Z = 50 W).
VCC
50 W 50 W
Q
Z
CLK
CML
or
VCC VTCLK
NB7L111M
VCC VTCLK
Z
Q CLK
VEE
Figure 18. CML to CML Interface
50 W
CML
or
NB7L111M
50 W
VEE
VCC
VCC
Recommended RT Values
VCC RT
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
PECL
Driver
50 W
Z
50 W
Z
RT RT
CLK
VBIAS*
VBIAS*
VTCLK
VTCLK
CLK
VEE
VEE
Figure 19. PECL to CML Receiver Interface
*VBIAS is within VCMR Range.
50 W NB7L111M
50 W
VEE
VCC
VCC
LVDS
Driver
Z CLK
VTCLK
50 W NB7L111M
VTCLK
50 W
Z
CLK
VEE
Figure 20. LVDS to CML Receiver Interface
VEE
http://onsemi.com
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| PDF Descargar | [ Datasheet NB7L111M.PDF ] | |
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