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PDF NB7L216 Data sheet ( Hoja de datos )

Número de pieza NB7L216
Descripción High Gain Receiver/Buffer/Translator
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No Preview Available ! NB7L216 Hoja de datos, Descripción, Manual

NB7L216
2.5V/3.3V, 12Gb/s Multi
Level Clock/Data Input to
RSECL, High Gain
Receiver/Buffer/Translator
with Internal Termination
Description
The NB7L216 is a differential receiver/driver with high gain output
targeted for high frequency applications. The device is functionally
equivalent to the NBSG16 but with much higher gain output. This
highly versatile device provides 35 dB of gain up to 7 GHz.
Inputs incorporate internal 50 W termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are Reduced Swing ECL (RSECL), 400 mV.
The VBB pin is an internally generated voltage supply available to
this device only. VBB is used as a reference voltage for single−ended
NECL or PECL inputs. For all single−ended input conditions, the
unused complementary differential input should be connected to VBB
as a switching reference voltage. VBB may also rebias AC coupled
inputs. When used, decouple VBB via a 0.01 mF capacitor and limit
current sourcing or sinking to 0.5 mA. When not used, VBB output
should be left open.
www.DataSheet4U.com
Application notes, models and support documentation are available
at www.onsemi.com.
Features
High Gain of 35 dB from DC to 7 GHz Typical
High IIP3: 0 dBm Typical
20 mV Minimum Input Voltage Swing
Maximum Input Clock Frequency up to 8.5 GHz
Maximum Input Data Rate up to 12 Gb/s Typical
<0.5 ps of RMS Clock Jitter
<9 ps of Data Dependent Jitter
120 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with Operating
Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak−to−Peak Output),
50 W Internal Input Termination Resistors (Temperature−Coefficient
of < 6.38 mW/°C)
VBB – ECL Reference Voltage Output
Pb−Free Packages are Available
http://onsemi.com
MARKING DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
16
1
NB7L
216
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
50 W
D
D
Q
Q
50 W
VTD
Figure 1. Functional Block Diagram
Device DDJ = 3 ps
TIME (17 ps/div)
Figure 2. Typical Output Waveform at
12 Gb/s with PRBS 223−1 (VINPP = 400 mV,
Input Signal DDJ = 12 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 2
1
Publication Order Number:
NB7L216/D

1 page




NB7L216 pdf
NB7L216
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, VEE = 0 V; (Note 12)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@ VINPPmin)fin 7.0 GHz 275 380
(See Figure 4)
fin 8.5 GHz 100 250
275 380
100 250
275 380
100 250
mV
fDATA Maximum Operating Data Rate
10 12
10 12
10 12
Gb/s
|S21| Power Gain DC to 7 GHz
35 35
35 dB
|S11| Input Return Loss @ 7 GHz
−10 −10
−10 dB
|S22| Output Return Loss @ 7 GHz
−5 −5
−5 dB
|S12| Reverse Isolation (Differential Configuration)
−25
−25
−25 dB
IIP3 Input Third Order Intercept
00
0 dBm
tPLH,
tPHL
tSKEW
Propagation Delay to Output Differential @ 1 GHz
Duty Cycle Skew (Note 12)
Device to Device Skew (Note 17)
60 120 180 60 120 180 60 120 180 ps
2 10
5 20
2 10
5 20
2 10 ps
5 20
tJITTER
RMS Random Clock Jitter
(Note 15)
fin v 8.5 GHz
Peak−to−Peak Data Dependent Jitter (Note 16)
fDATA = 3.5 Gb/s
fDATA = 5.0 Gb/s
fDATA = 10 Gb/s
fDATA = 12 Gb/s
0.1 0.5
17
39
49
49
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14 and Figure 12)
20
2500 20
0.1 0.5
17
39
49
49
2500 20
0.1 0.5 ps
17
39
49
49
2500 mV
tr Output Rise/Fall Times @ 0.5 GHz Q, Q
tf (20% − 80%)
30 45
30 45
30 45 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing VINPPmin from a 50% duty cycle clock source. All loading with an external RL = 50 W to VTT =VCC − 2.0 V. Input edge
rates 40 ps (20% − 80%).
13. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.
14. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
15. Additive RMS jitter with 50% duty cycle clock signal.
16. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 223−1.
17. Device to device skew is measured between outputs under identical transition @ 1 GHz.
500
450
400 −40°C
350
85°C
300
250
25°C
200
150
100
50
0
0 2 4 6 7 8 9 10 11 12
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fIN) and Temperature
(VINPP = 400 mV, VCC = 3.3 V and VEE = 0 V)
500
450
400
−40°C
350
300
250 85°C
200 25°C
150
100
50
0
0 2 4 6 7 8 9 10 11 12
INPUT CLOCK FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fIN) and Temperature
(VINPP = 20 mV, VCC = 3.3 V and VEE = 0 V)
http://onsemi.com
5

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NB7L216 arduino
NB7L216
ORDERING INFORMATION
Device
Package
Shipping
NB7L216MN
QFN−16
123 Units / Rail
NB7L216MNG
QFN−16
(Pb−Free)
123 Units / Rail
NB7L216MNR2
QFN−16
3000 / Tape & Reel
NB7L216MNR2G
QFN−16
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
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