NB7N017M PDF даташит
Спецификация NB7N017M изготовлена «ON Semiconductor» и имеет функцию, называемую «3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler». |
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Детали детали
Номер произв | NB7N017M |
Описание | 3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler |
Производители | ON Semiconductor |
логотип |
19 Pages
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NB7N017M
3.3 V SiGe 8‐Bit Dual
Modulus Programmable
Divider/Prescaler with CML
Outputs
Description
The NB7N017M is a high speed 8-bit dual modulus programmable
divider/prescaler with 16 mA CML outputs capable of switching at
input frequencies greater than 3.5 GHz. The CML output structure
contains internal 50 W source termination resistor to VCC. The
device generates 400 mV output amplitude with 50 W receiver
resistor to VCC. This I/O structure enables easy implementation of
the NB7N017M in 50 W systems.
The differential inputs contain 50 W termination resistors to VT
pads and all differential inputs accept RSECL, ECL, LVDS,
LVCMOS, LVTTL, and CML.
Internally, the NB7N017M uses a > 3.5 GHz 8-bit programmable
down counter. A select pin, SEL, is used to select between two
words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb
respectively. Two parallel load pins, PLa and PLb, are used to load
the level triggered programming registers, REGa and REGb,
respectively. A differential clock enable, CE, pin is available.
The NB7N017M offers a differential output, TC. Terminal count
output, TC, goes high for one clock cycle when the counter has
reached the all zeros state. To reduce output phase noise, TC is
retimed with the rising edge triggered latches.
Features
• Maximum Input Clock Frequency > 3.5 GHz Typical
• Differential CLK Clock Input
• Differential CE Clock Enable Input
• Differential SEL Word Select Input
• 50 W Internal Input and Output Termination Resistors
• Differential TC Terminal Count Output
• All Outputs 16 mA CML with 50 W Internal Source Termination
to VCC
• All Single-Ended Control Pins CMOS and PECL/NECL Compatible
• Counter Programmed Using One of Two Single-Ended Words,
Pa[0:7] and Pb[0:7], Stored in REGa and REGb
• REGa and REGb Implemented with Level Triggered Latch
• Compatible with Existing 3.3 V LVEP, EP, and SG Devices
• Ability to Program the Divider without Disturbing Current Settings
• Positive CML Output Operating Range:
♦ VCC = 3.0 V to 3.465 V with VEE = 0 V
• Negative CML Output Operating Range:
♦ VCC = 0 V with VEE = –3.0 V to –3.465 V
• VBB Reference Voltage Output
• CML Output Level: 400 mV Peak-Peak Output with 50 W Receiver
Resistor to VCC
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
1 52
QFN−52
MN SUFFIX
CASE 485M−01
MARKING DIAGRAM*
52
1
NB7N
017M
AWLYYWWG
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
NB7N017MMNG
NB7N017MMNR2G
Package Shipping†
QFN−52 260 Tray JEDEC
(Pb-Free)
QFN−52 2000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 5
1
Publication Order Number:
NB7N017M/D
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VCC 1
PLa 2
Pa0 3
Pa1 4
Pa2 5
VCC 6
Pa3 7
VEE 8
Pa4 9
Pa5 10
Pa6 11
Pa7 12
NC 13
NB7N017M
NB7N017M
Figure 1. Pinout (Top View)
Exposed Pad (EP)
39 VEE
38 PLb
37 Pb0
36 Pb1
35 Pb2
34 VCC
33 Pb3
32 VEE
31 Pb4
30 Pb5
29 Pb6
28 Pb7
27 NC
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NB7N017M
Table 1. PIN DESCRIPTION
Pin Name
Default Single/Differential
I/O
State
(Notes 1 and 2)
Description
CLK
ECL, CML, LVCMOS,
−
LVDS, LVTTL Input
Differential
Clock
CE
ECL, CML, LVCMOS,
−
Differential
Clock Enable
LVDS, LVTTL Input
MR
CMOS, ECL Input
Low
Single
Asynchronous Master Reset: Counter set to 0000 0000 to
reload at next CLK pulse, REGa and REGb = 1111 1111 and
TC = 1.
SEL
ECL, CML, LVCMOS,
−
LVDS, LVTTL Input
Differential
Divide Select
PLa, PLb
CMOS, ECL Input
Low
Single
Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level
Triggered)
TC
Pa[0:7], Pb[0:7]
CML Output
CMOS, ECL Input
−
High
Differential
Single
Terminal Count, 16 mA CML output with 50 W Source
Termination to VCC (Note 5)
Counter Program Pins. CMOS and PECL/NECL compatible
Pa7 = MSB, Pb7 = MSB
VCC
VEE
VTCLK, VTCLK,
VTSEL, VTSEL
VTCE, VTCE
Power
Power
Termination
− − Positive Supply
− − Negative Supply
−
Differential
50 W Internal Input Termination Resistor (Note 6)
VBB
Output
−
− CMOS/ECL Reference Voltage Output
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑNC N/A − − No Connect (Note 4)
EP − − − Exposed Pad (Note 3)
1. All high speed inputs and outputs are differential to improve performance.
2. All single-ended inputs are CMOS and NECL/ECL compatible.
3. All VCC and VEE pins must be externally connected to external power supply voltage to guarantee proper device operation. The thermally
exposed pad (EP) on package bottom (see case drawing) must be attached to a heat-sinking conduit. Exposed pad is bonded to the lowest
voltage potential, VEE.
4. The NC pins are electrically connected to the die and must be left open.
5. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied
then the device will be susceptible to self-oscillation.
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Номер в каталоге | Описание | Производители |
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