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PDF WM8718 Data sheet ( Hoja de datos )

Número de pieza WM8718
Descripción 24 Bit Differential Stereo DAC
Fabricantes Wolfson Microelectronics 
Logotipo Wolfson Microelectronics Logotipo



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WM8718
24 Bit Differential Stereo DAC with Volume Control
DESCRIPTION
FEATURES
The WM8718 is a high performance differential stereo DAC
designed for audio applications such as DVD, home theatre
systems and digital TV. The WM8718 supports PCM data
input word lengths from 16 to 32-bits and sampling rates up
to 192kHz. The WM8718 consists of a serial interface port,
digital interpolation filters, multi-bit sigma delta modulators
and differential stereo DAC in a small 20-lead SSOP
package or 24-lead QFN package. The WM8718 includes a
digitally controllable mute, an attenuate function and zero
flag output for each channel.
The 3-wire serial control port provides access to a wide
range of features including on-chip mute, attenuation and
phase reversal.
The WM8718 is an ideal device to interface to AC-3,
DTS, and MPEG audio decoders for surround sound
applications, or for use in DVD players including those
supporting DVD-A.
24 bit Stereo DAC
Fully Differential Voltage Outputs
Audio Performance
- 111dB SNR (‘A’ weighted @ 48kHz) DAC
- -100dB THD
DAC Sampling Frequency: 8kHz - 192kHz
3 Wire Serial Control Interface
Programmable Audio Data Interface Modes
- I2S, Left, Right Justified, DSP
- 16/20/24/32 bit Word Lengths
Independent Digital Volume Control on Each Channel with
127.5dB Range in 0.5dB Steps
Independent Zero Flag Outputs
3.0V - 5.5V Supply Operation
20-lead SSOP Package or 24-lead QFN Package
APPLICATIONS
BLOCK DIAGRAM
CD, DVD, and DVD-Audio Players
Home theatre systems
www.DataSheet4U.comProfessional mixing desks
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WM8718
CONTROL
INTERFACE
ZEROFR
ZEROFL
BCKIN
LRCIN
DIN
AUDIO
INTERFACE
ATT/
MUTE
ATT/
MUTE
DIGITAL
FILTERS
SIGMA
DELTA
MODULATOR
SIGMA
DELTA
MODULATOR
DAC
DAC
VOUTRP
VOUTRN
VOUTLP
VOUTLN
VMID
WOLFSON MICROELECTRONICS plc
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Production Data, November 2006, Rev 4.3
Copyright ©2006 Wolfson Microelectronics plc

1 page




WM8718 pdf
WM8718
Production Data
PIN DESCRIPTION – 20 LEAD SSOP
PIN NAME
TYPE
DESCRIPTION
1 LRCIN
Digital Input
PCM DAC Sample Rate Clock Input
2 DVDD
Supply
Positive Digital Supply
3 DGND
Supply
Ground Digital Supply
4 AVDD
Supply
Positive Analogue Supply
5 VREFP
Supply
Positive DAC reference Supply
6 VREFN
Supply
Negative DAC reference Supply
7 AGND
Supply
Ground Analogue Supply
8 VMID
Analogue Output
Mid Rail Decoupling Point
9 VOUTRP
Analogue Output
Right Channel DAC Output Positive
10 VOUTRN
Analogue Output
Right Channel DAC Output Negative
11 VOUTLN
Analogue Output
Left Channel DAC Output Negative
12 VOUTLP
Analogue Output
Left Channel DAC Output Positive
13 LATCH
Digital Input P.U.
Serial Control Load Input
14 SDIN
Digital Input
Serial Control Data Input
15 SCLK
Digital Input P.D.
Serial Control Data Input Clock
16
ZEROFR
Digital Output (Open drain) Infinite ZERO Detect Flag for Right Channel
17
ZEROFL
Digital Output (Open drain) Infinite ZERO Detect Flag for Left Channel
18 MCLK
Digital Input
Master Clock Input
19 BCLKIN
Digital Input
PCM Audio Data Bit Clock Input
20 DIN
Digital Input
PCM Serial Audio Data Input
Note:
Digital input pins have Schmitt trigger input buffers. Pins marked `P.U.` or `P.D.` have an internal pull-up or pull-down resistor.
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PD Rev 4.3 November 2006
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WM8718 arduino
WM8718
3-WIRE SERIAL CONTROL INTERFACE TIMING
LATCH
SCLK
tSCY
tSCH
tSCL
Production Data
tCSL
tCSH
tCSS
tSCS
SDIN
tDSU
tDHO
LSB
Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Program Register Input Information
SCLK rising edge to LATCH
rising edge
tSCS
SCLK pulse cycle time
tSCY
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
tSCL
tSCH
tDSU
tDHO
LATCH pulse width low
LATCH pulse width high
LATCH rising to SCLK rising
tCSL
tCSH
tCSS
TEST CONDITIONS
MIN TYP MAX
40
80
20
20
20
20
20
20
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
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PD Rev 4.3 November 2006
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