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PDF WM8781 Data sheet ( Hoja de datos )
| Número de pieza | WM8781 | |
| Descripción | Stereo ADC | |
| Fabricantes | Wolfson Microelectronics | |
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24-Bit, 192kHz Stereo ADC
WM8781
DESCRIPTION
The WM8781 is a high performance, low cost stereo audio
ADC designed for recordable media applications.
The device offers stereo line level inputs along with two
control input pins (FORMAT, IWL) to allow operation of the
audio interface in three industry standard modes. An
internal op-amp is integrated on the front end of the chip to
accommodate analogue input signals greater than 1Vrms.
The device also has a high pass filter to remove residual
DC offsets.
WM8781 offers Master or Slave mode clocking schemes.
A control input pin M/S is used to allow Slave mode
operation or Master mode operation. A stereo 24-bit multi-
bit sigma-delta ADC is used with 128x, 64x or 32x over-
sampling, according to sample rate. Digital audio output
word lengths from 16-24 bits and sampling rates from 8kHz
to 192kHz are supported.
The device is a hardware controlled device and is supplied
in a 20-lead SSOP package.
BLOCK DIAGRAM
FEATURES
SNR 102dB (‘A’ weighted @ 48kHz)
THD -90dB (at –1dB)
Sampling Frequency: 8 – 192kHz
Master or Slave Clocking Mode
System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs
Audio Data Interface Modes
- 16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified
Supply Voltages
- Analogue 2.7 to 5.5V
- Digital core: 2.7V to 3.6V
20-lead SSOP package
APPLICATIONS
Recordable DVD Players
Personal Video Recorders
STB
Studio Audio Processing Equipment
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews
Production Data, January 2012, Rev 4.5
Copyright 2012 Wolfson Microelectronics plc
1 page  
Production Data
WM8781
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating
at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under
Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Ambient temperature (supplies applied)
Storage temperature after soldering
Pb free package body temperature (reflow 10 seconds)
Package body temperature (soldering 2 minutes)
Notes
1. Analogue and digital grounds must always be within 0.3V of each other.
MIN
-0.3V
-0.3V
DGND -0.3V
AGND -0.3V
-55oC
-65C
MAX
+4.5V
+7V
DVDD + 0.3V
AVDD +0.3V
+125oC
+150C
+260oC
+183oC
THERMAL PERFORMANCE
PARAMETER
SYMBOL
TEST CONDITIONS MIN TYP MAX
SSOP-20 package
Thermal resistance – junction to
ambient
RθJA
81
See note 1
Notes:
1. Figure given for package mounted on 4-layer FR4 according to JESD51-7. (No forced air flow is assumed).
2. Thermal performance figures are estimated.
UNIT
°C/W
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
Digital supply range
DVDD
Analogue supply range
AVDD
Ground
DGND,AGND
Operating temperature range
TA
Notes
1. Digital supply DVDD must never be more than 0.3V greater than AVDD.
MIN
2.7
2.7
-25C
TYP
MAX
3.6
5.5
0
+85C
UNIT
V
V
V
V
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PD, January 2012, Rev 4.5
5
5 Page 
Production Data
WM8781
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
DOUT: ADC data output
LRCLK: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT
and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with
left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left
or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always
an output. BCLK and LRCLK maybe an inputs or outputs depending whether the device is in Master
or Slave mode. (see Master and Slave Mode Operation, below).
Three different audio data formats are supported:
Left justified
Right justified
I2S
MASTER AND SLAVE MODE OPERATION
The WM8781 can be configured as either a master or slave mode device. As a master device the
WM8781 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT. In
slave mode, the WM8781 responds with data to clocks it receives over the digital audio interface. The
mode can be selected by setting the MS input pin (see Table 4 Master/Slave selection below).
Master and slave modes are illustrated below.
Figure 5 Master Mode
Figure 6 Slave Mode
PIN
M/S
DESCRIPTION
Master/Slave Selection
0 = Slave Mode
1= Master Mode
Table 4 Master/Slave selection
AUDIO INTERFACE CONTROL
The Input Word Length and Audio Format mode can be selected by using IWL and FORMAT pins.
PIN
IWL
FORMAT
DESCRIPTION
Word Length
0 = 16 bit
1 = 20 bit
Z = 24 bit
Audio Mode Select
0 = RJ
1 = LJ
Z = I2S
Table 5 Audio Data Format Control
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PD, January 2012, Rev 4.5
11
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| PDF Descargar | [ Datasheet WM8781.PDF ] | |
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