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PDF NCP1653 Data sheet ( Hoja de datos )
| Número de pieza | NCP1653 | |
| Descripción | Continuous Conduction Mode PFC Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP1653, NCP1653A
Compact, Fixed-Frequency,
Continuous Conduction
Mode PFC Controller
The NCP1653 is a controller designed for Continuous Conduction
Mode (CCM) Power Factor Correction (PFC) boost circuits. It
operates in the follower boost or constant output voltage in 67 or 100
kHz fixed switching frequency. Follower boost offers the benefits of
reduction of output voltage and hence reduction in the size and cost
of the inductor and power switch. Housed in a DIP−8 or SO−8
package, the circuit minimizes the number of external components
and drastically simplifies the CCM PFC implementation. It also
integrates high safety protection features. The NCP1653 is a driver
for robust and compact PFC stages.
Features
• IEC1000−3−2 Compliant
• Continuous Conduction Mode
• Average Current−Mode or Peak Current−Mode Operation
• Constant Output Voltage or Follower Boost Operation
• Very Few External Components
• Fixed Switching Frequency: 67 kHz = NCP1653A,
Fixed Switching Frequency: 100 kHz = NCP1653
• Soft−Start Capability
• VCC Undervoltage Lockout with Hysteresis (8.7 / 13.25 V)
• Overvoltage Protection (107% of Nominal Output Level)
• Undervoltage Protection or Shutdown (8% of Nominal Output Level)
• Programmable Overcurrent Protection
• Programmable Overpower Limitation
• Thermal Shutdown with Hysteresis (120 / 150_C)
• This is a Pb−Free Device
Typical Applications
• TV & Monitors
• PC Desktop SMPS
• AC Adapters SMPS
• White Goods
AC
Input
EMI
Filter
Output
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MARKING DIAGRAMS
8
1
PDIP−8
P SUFFIX
CASE 626
8
1
SO−8
D SUFFIX
CASE 751
8
NCP1653
AWL
YYWWG
1
8
NCP1653A
AWL
YYWWG
1
8
N1653
ALYW
G
1
8
1653A
ALYW
G
1
A suffix = 67 kHz option
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
PIN CONNECTIONS
FB 1
8 VCC
Vcontrol 2
7 Drv
In 3
6 GND
CS 4
5 VM
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
15 V
FB VCC
Vcontrol Drv
In Gnd
CS VM
NCP1653
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 10
1
Publication Order Number:
NCP1653/D
1 page  
NCP1653, NCP1653A
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C. For min/max values, TJ = −40°C to +125°C, VCC = 15 V,
IFB = 100 mA, Ivac = 30 mA, IS = 0 mA, unless otherwise specified)
Characteristics
Pin Symbol Min Typ Max Unit
SUPPLY SECTION
Supply Voltage
UVLO Startup Threshold
Minimum Operating Voltage after Startup
UVLO Hysteresis
8
VCC(on)
VCC(off)
VCC(H)
12.25
8.0
4.0
13.25
8.7
4.55
14.5
9.5
−
V
V
V
Supply Current:
Startup (VCC = VCC(on) − 0.2 V)
Startup (VCC < 8.0 V, IFB = 200 mA)
Startup (8.0 V < VCC < VCC(on) − 0.2 V, IFB = 200 mA)
Startup (VCC < VCC(on) − 0.2 V, IFB = 0 mA) (Note 5)
Operating (VCC = 15 V, Drv = open, VM = 3 V)
Operating (VCC = 15 V, Drv = 1 nF to Gnd, VM = 1 V)
Shutdown (VCC = 15 V and IFB = 0 A)
8
Istup
Istup1
Istup2
Istup3
ICC1
ICC2
Istdn
− 18 50 mA
− 0.95 1.5 mA
− 21 50 mA
− 21 50 mA
− 3.7 5.0 mA
− 4.7 6.0 mA
− 33 50 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Please refer to the “Biasing the Controller” Section in the Functional Description.
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5
5 Page 
NCP1653, NCP1653A
The input filter capacitor Cfilter and the front−ended EMI
filter absorbs the high−frequency component of inductor
current IL. It makes the input current Iin a low−frequency
signal only of the inductor current.
Iin + IL−50
(eq.2)
The suffix 50 means it is with a 50 or 60 Hz bandwidth
of the original IL.
From (eq.1) and (eq.2), the input impedance Zin is
formulated.
Zin
+
Vin
Iin
+
T
*
T
t1
Vout
IL−50
(eq.3)
Power factor is corrected when the input impedance Zin
in (eq.3) is constant or slowly varying in the 50 or 60 Hz
bandwidth.
Ich
Cramp
01
VM Vref
PFC Modulation
−
++
RQ
Vramp
S
clock
Vref
Vramp
VM
VM
without
filtering
Clock
Latch Set
Latch Reset
Output
Inductor
Current
Figure 27. PFC Duty Modulation and Timing Diagram
The PFC duty modulation and timing diagram is shown
in Figure 27. The MOSFET on time t1 is generated by the
intersection of reference voltage Vref and ramp voltage
Vramp. A relationship in (eq.4) is obtained.
Vramp
+
VM
)
Icht1
Cramp
+
Vref
(eq.4)
The charging current Ich is specially designed as in
(eq.5). The multiplier voltage VM is therefore expressed in
terms of t1 in (eq.6).
Ich
+
Cramp
T
Vref
(eq.5)
VM
+
Vref
*
t1
Cramp
CrampVref
T
+
Vref
T
*
T
t1
(eq.6)
From (eq.3) and (eq.6), the input impedance Zin is
re−formulated in (eq.7).
Zin
+
VM
Vref
Vout
IL−50
(eq.7)
Because Vref and Vout are roughly constant versus time,
the multiplier voltage VM is designed to be proportional to
the IL−50 in order to have a constant Zin for PFC purpose.
It is illustrated in Figure 28.
V in
I in time
IL
time
VM
time
Figure 28. Multiplier Voltage Timing Diagram
It can be seen in the timing diagram in Figure 27 that VM
originally consists of a switching frequency ripple coming
from the inductor current IL. The duty ratio can be
inaccurately generated due to this ripple. This modulation
is the so−called “peak current−mode”. Hence, an external
capacitor CM connected to the multiplier voltage VM pin
(Pin 5) is essential to bypass the high−frequency
component of VM. The modulation becomes the so−called
“average current−mode” with a better accuracy for PFC.
VM 5
IM
CM RM
VM =
RM Ivac IS
2Icontrol
PFC Duty
Modulation
Figure 29. External Connection on the Multiplier
Voltage Pin
The multiplier voltage VM is generated according to
(eq.8).
VM
+
RM Ivac IS
2 Icontrol
(eq.8)
Input−voltage current Ivac is proportional to the RMS
input voltage Vac as described in (eq.9). The suffix ac
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11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet NCP1653.PDF ] | |
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