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PDF NCP5218 Data sheet ( Hoja de datos )
| Número de pieza | NCP5218 | |
| Descripción | 2-in-1 Notebook DDR Power Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP5218
2−in−1 Notebook DDR
Power Controller
The NCP5218 2−in−1 Notebook DDR Power Controller is
specifically designed as a total power solution for notebook DDR
memory system. This IC combines the efficiency of a PWM
controller for the VDDQ supply with the simplicity of linear
regulators for the VTT termination voltage and the buffered low noise
reference. This IC contains a synchronous PWM buck controller for
driving two external NFETs to form the DDR memory supply
voltage (VDDQ). The DDR memory termination regulator output
voltage (VTT) and the buffered VREF are internally set to track at the
half of VDDQ. An internal power good voltage monitor tracks VDDQ
output and notifies the user whether the VDDQ output is within target
range. Protective features include soft−start circuitries, undervoltage
monitoring of supply voltage, VDDQ overcurrent protection, VDDQ
overvoltage and undervoltage protections, and thermal shutdown.
The IC is packaged in DFN22.
Features
• Incorporates VDDQ, VTT Regulator, Buffered VREF
• Adjustable VDDQ Output
• VTT and VREF Track VDDQ/2
• Operates from Single 5.0 V Supply
• Supports VDDQ Conversion Rails from 4.5 V to 24 Vwww.DataSheet4U.com
• Power−saving Mode for High Efficiency at Light Load
• Integrated Power FETs with VTT Regulator Sourcing/Sinking
1.5 A DC and 2.4 A Peak Current
• Requires Only 20 mF Ceramic Output Capacitor for VTT
• Buffered Low Noise 15 mA VREF Output
• All External Power MOSFETs are N−channel
• <5.0 mA Current Consumption During Shutdown
• Fixed Switching Frequency of 400 kHz
• Soft−start Protection for VDDQ and VTT
• Undervoltage Monitor of Supply Voltage
• Overvoltage Protection and Undervoltage Protection for VDDQ
• Short−circuit Protection for VDDQ and VTT
• Thermal Shutdown
• Housed in DFN22
• This is a Pb−Free Device
Typical Applications
• Notebook DDR/DDR2 Memory Supply and Termination Voltage
• Active Termination Busses (SSTL−18, SSTL−2, SSTL−3)
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MARKING
DIAGRAM
22
DFN22
MN SUFFIX
1
NCP5218
CASE 506AF
AWLYYWW
1G
NCP5218= Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
PIN CONNECTIONS
VDDQEN
VTTEN
FPWM
SS
VTTGND
VTT
VTTI
FBVTT
AGND
DDQREF
VCCA
(Top View)
PGND
BGDDQ
VCCP
SWDDQ
TGDDQ
BOOST
OCDDQ
PGOOD
VTTREF
FBDDQ
COMP
NOTE: Pin 23 is the thermal pad on
the bottom of the device.
ORDERING INFORMATION
Device
Package
Shipping†
NCP5218MNR2G DFN22 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 0
1
Publication Order Number:
NCP5218/D
1 page  
NCP5218
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage (Pin 11, 20) to AGND (Pin 9)
High−Side Gate Drive Supply: BOOST (Pin 17) to SWDDQ (Pin 19)
Input/Output Pins to AGND (Pin 9)
Pins 1−4, 6−8, 10, 12−15
VCCA, VCCP
VBOOST−VSWDDQ
VIO
−0.3, 6.0
−0.3, 6.0
−0.3, 6.0
V
V
V
Overcurrent Sense Input (Pin 16) to AGND (Pin 9)
Switch Node (Pin 19)
VOCDDQ
VSWDDQ
27
−4.0 (<100 ns),
−0.3 (dc), 32
V
V
High−Side FET Gate Drive Voltage: TGDDQ (Pin 18) To SWDDQ (Pin 19)
Low−Side FET Gate Drive Voltage: BGDDQ (Pin 21) To PGND (Pin 22)
VTGDDQ −
VSWDDQ
VBGDDQ
−2.0 (< 100 ns)
−0.3 (dc), 6.0
−2.0 (< 100 ns)
−0.3 (dc), 6.0
V
V
PGND (Pin 22), VTTGND (Pin 5) to AGND (Pin 9)
Thermal Characteristics
DFN22 Plastic Package
Thermal Resistance, Junction−to−Ambient
VGND
RqJA
−0.3, 0.3
35
V
_C/W
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
TJ
TA
Tstg
MSL
0 to +150
−40 to +85
−55 to +150
1
_C
_C
_C
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ≤2.0 kV per JEDEC standard: JESD22–A114 except Pin 17 which is ≤ 1 kV.
Machine Model (MM) ≤200 V per JEDEC standard: JESD22–A115 except Pin 17 which is ≤ 150 V.
2. Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78.
3. Pin 16 (OCDDQ) must be pulled high to VIN through a resistor.
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5
5 Page 
100
90
80
70
60
50
0.1
NCP5218
TYPICAL OPERATING CHARACTERISTICS
100
VIN = 5 V
VIN = 12 V
VIN = 20 V
with power−saving
without power−saving
90
80
70
VIN = 5 V
VIN = 12 V
VIN = 20 V
with power−saving
without power−saving
VDDQ = 2.5 V
Freq = 400 kHz max
TA = 25°C
1.0 10 100
IVDDQ, VDDQ OUTPUT CURRENT (A)
Figure 15. VDDQ Efficiency (DDR)
vs. VDDQ Output Current
60
50
0.1
VDDQ = 1.8 V
Freq = 400 kHz max
TA = 25°C
1.0 10 100
IVDDQ, VDDQ OUTPUT CURRENT (A)
Figure 16. VDDQ Efficiency (DDR2)
vs. VDDQ Output Current
VIN
VDDQ
20V/div
1V/div
VTT 1V/div
VTTR
1V/div
VDDQEN = High; VTTEN = High; VIN = 0 V to 20 V
Figure 17. Powerup Waveforms
VDDQEN
VDDQ
5V/div
1V/div
VTTR
PGOOD
1V/div
5V/div
VIN
VDDQ
20V/div
1V/div
VTT 1V/div
VTTR
1V/div
VDDQEN = High; VTTEN = High; VIN =20 V to 0 V
Figure 18. Powerdown Waveforms
VDDQEN
VDDQ
5V/div
1V/div
VTTR
PGOOD
1V/div
5V/div
VDDQEN = 0 V to 5 V
Figure 19. VDDQ, VTTR Startup Waveforms
VDDQEN = 5 V to 0 V
Figure 20. VDDQ, VTTR Shutdown Waveforms
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11
11 Page | ||
| Páginas | Total 31 Páginas | |
| PDF Descargar | [ Datasheet NCP5218.PDF ] | |
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