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PDF NL17SZ126 Data sheet ( Hoja de datos )
| Número de pieza | NL17SZ126 | |
| Descripción | Non-Inverting 3-State Buffer | |
| Fabricantes | ON Semiconductor | |
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NL17SZ126
Non-Inverting 3-State
Buffer
The NL17SZ126 is a high performance single noninverting buffer
operating from a 1.65 V to 5.5 V supply.
Features
• Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5.0 V
• Designed for 1.65 V to 5.5 V VCC Operation
• Over Voltage Tolerant Inputs and Outputs
• LVTTL Compatible − Interface Capability With 5.0 V TTL Logic
with VCC = 3.0 V
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current Substantially Reduces System
Power Requirements
• 3−State OE Input is Active HIGH
• Replacement for NC7SZ126
• Chip Complexity = 36 FETs
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
OE
1
IN A
2
GND
3
VCC
A
51
GND
2
OUT Y
4
OE
3
VCC
5
Y
4
SOT−353/SC−88A/ SOT−553
SOT−953
Figure 1. Pinout (Top View)
www.onsemi.com
MARKING
DIAGRAM
SC−88A (SOT−353)
DF SUFFIX
CASE 419A
M2 M G
G
SOT−553
XV5 SUFFIX
CASE 463B
M2 MG
G
SOT−953
CASE 527AE
M
1
M2 or R = Specific Device Code
(R with 180 degree clockwise rotation)
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
OE
OUT Y
IN A
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2015
September, 2016 − Rev. 14
1
Publication Order Number:
NL17SZ126/D
1 page  
NL17SZ126
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical Unit
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(Note 6)
VCC = 5.5 V, VI = 0 V or VCC
VCC = 5.5 V, VI = 0 V or VCC
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
10 MHz, VCC = 5.5 V, VI = 0 V or VCC
2.5 pF
2.5 pF
9 pF
11
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
A
tPLH
50%
50% VCC
Y
VCC
GND
tPHL
INPUT
OE = VCC
CL*
OUTPUT
RL
Figure 4. Switching Waveform
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended for
propagation delay tests.
Figure 5. tPLH or tPHL
2 VCC
INPUT
R1 = 500 W
OUTPUT
CL = 50 pF RL = 500 W
INPUT
VCC
OUTPUT
CL = 50 pF RL = 250 W
A 1−MHz square input wave is recommended for
propagation delay tests.
Figure 6. tPZL or tPLZ
OE
tPZH
On
Vmi
tPHZ
Vmo
tPZL
On
tPLZ
Vmo
A 1−MHz square input wave is recommended for
propagation delay tests.
Figure 7. tPZH or tPHZ
2.7 V
Vmi
0V
VCC
VOH − 0.3 V
≈0V
≈ 3.0 V
VOL + 0.3 V
GND
Figure 8. AC Output Enable and Disable Waveform
www.onsemi.com
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet NL17SZ126.PDF ] | |
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