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PDF NSTB1005DXV5T5 Data sheet ( Hoja de datos )
| Número de pieza | NSTB1005DXV5T5 | |
| Descripción | (NSTB1005DXV5T1 / NSTB1005DXV5T5) Dual Common Base-Collector Bias Resistor Transistors | |
| Fabricantes | ON Semiconductor | |
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NSTB1005DXV5T1,
NSTB1005DXV5T5
Preferred Devices
Dual Common
Base−Collector Bias
Resistor Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. The NSTB1005DXV5T1
contains two complementary BRT devices are housed in the SOT−553
package which is ideal for low power surface mount applications
where board space is at a premium.
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch Tape and Reel
• Lead Free
www.DataSheet4U.com
MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1
and Q2, − minus sign for Q1 (PNP) omitted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
VCBO
VCEO
IC
50 Vdc
50 Vdc
100 mAdc
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C
Derate above 25°C
PD
357 (Note 1) mW
2.9 (Note 1) mW/°C
Thermal Resistance −
Junction-to-Ambient
RqJA 350 (Note 1) °C/W
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C
Derate above 25°C
PD
500 (Note 1) mW
4.0 (Note 1) mW/°C
Thermal Resistance −
Junction-to-Ambient
RqJA 250 (Note 1) °C/W
Junction and Storage Temperature
1. FR−4 @ Minimum Pad
TJ, Tstg − 55 to +150
°C
http://onsemi.com
32
R1 R2
1
Q1
4
R2
R1
Q2
5
5
1
SOT−553
CASE 463B
MARKING DIAGRAM
5
UC D
1
UC = Specific Device Code
D = Date Code
ORDERING INFORMATION
Device
Package Shipping†
NSTB1005DXV5T1 SOT−553 4 mm pitch
4000/Tape & Reel
NSTB1005DXV5T5 SOT−553 2 mm pitch
8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 0
1
Publication Order Number:
NSTB1005DXV5/D
1 page  
NSTB1005DXV5T1, NSTB1005DXV5T5
PACKAGE DIMENSIONS
SOT−553
XV5 SUFFIX
5−LEAD PACKAGE
CASE 463B−01
ISSUE A
A
−X− C
54
12 3
B
−Y−
D 5 PL
G 0.08 (0.003) M X Y
K
S
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 1.50 1.70 0.059 0.067
B 1.10 1.30 0.043 0.051
C 0.50 0.60 0.020 0.024
D 0.17 0.27 0.007 0.011
G 0.50 BSC
0.020 BSC
J 0.08 0.18 0.003 0.007
K 0.10 0.30 0.004 0.012
S 1.50 1.70 0.059 0.067
SOLDERING FOOTPRINT*
0.3
0.0118
1.35
0.0531
1.0
0.0394
0.45
0.0177
0.5 0.5
0.0197 0.0197
ǒ ǓSCALE 20:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NSTB1005DXV5T5.PDF ] | |
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