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PDF CEU6060R Data sheet ( Hoja de datos )
| Número de pieza | CEU6060R | |
| Descripción | N-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | CET | |
| Logotipo |  |
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CED6060R/CEU6060R
Feb. 2003
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
60V , 30A , RDS(ON)=25mΩ @VGS=10V.
6 Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-251 & TO-252 package.
D
D
G
S
CEU SERIES
TO-252AA(D-PAK)
G
DS
CED SERIES
TO-251(l-PAK)
G
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous @TJ=125 C
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
VDS
VGS
ID
IDM
IS
PD
TJ, TSTG
Limit
60
ĆȀ20
30
120
30
50
0.3
-55 to 175
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
RįJC
RįJA
6-42
3
50
C/W
C/W
1 page  
CED6060R/CEU6060R
15
12 VDS=48V
ID=30A
9
300
100
RDS(ON)Limit
10ijs
100ijs
1ms
6
10
10ms
D1C00ms
3 VGS=10V
60
Single Pulse
Tc=25 C
1
0 6 12 18 24 30 36 42 48
1 10 60 100
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 9. Gate Charge
Figure 10. Maximum Safe
Operating Area
VDD
RL
VIN
D VOUT
VGS
RGEN G
S
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
2
1
D=0.5
0.2
0.1
0.1 0.05
0.02
0.01
Single Pulse
0.01
0.01
0.1
1 10 100
Square Wave Pulse Duration (msec)
PDM
t1
t2
1. RįJA (t)=r (t) * RįJA
2. RįJA=See Datasheet
3. TJM-TA = PDM* RįJA (t)
4. Duty Cycle, D=t1/t2
1000
10000
Figure 13. Normalized Thermal Transient Impedance Curve
6-46
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet CEU6060R.PDF ] | |
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