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PDF HI5828 Data sheet ( Hoja de datos )
| Número de pieza | HI5828 | |
| Descripción | Dual High Speed CMOS D/A | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HI5828
August 1999 File Number 4658.1
12-Bit, 125+MSPS, CommLink™ Dual High
Speed CMOS D/A (2.7V-5.5V)
The HI5828 is a Dual 12-bit, 125+MSPS (Mega Samples Per
Second), high speed, low power, D/A converter which is
implemented in an advanced CMOS process. Operating
from a single +3V to +5V supply, the converter provides
20mA of full scale output current and includes edge-triggered
CMOS input data latches. Low glitch energy and excellent
frequency domain performance is achieved by the HI5828’s
segmented current source architecture.
This device complements the CommLink HI5x60 and HI5x28
family of high speed converters, which includes 8, 10, 12,
and 14-bit devices
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC)
CLOCK
PACKAGE PKG. NO. SPEED
HI5828IN
-40 to 85 48 Ld LQFP Q48.7x7A 125MSPS
HI5828EVAL2 25 Evaluation Platform
125MSPS
Pinout
HI5828
(LQFP)
TOP VIEW
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . .125+MSPS
• Low Power . . . . 312mW at 5V, 46mW at 3V (at 60MSPS)
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.75 LSB (Typ)
• Adjustable Full Scale Output Current . . . . . . 2mA to 20mA
• Internal 1.2V Bandgap Voltage Reference
• Single or Dual Power Supply from +3V to +5V
• Power Down Mode
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(76dBc, fS = 50MSPS, fOUT = 2.51MHz)
• Excellent Multitone Intermodulation Distortion
Applications
• Basestations (Cellular, WLL)
• Quadrature Modulation
• Wireless Communications Systems
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Medical/Test Instrumentation
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
ID5
ID4
ID3
ID2
ID1
(LSB) ID0
N.C.
N.C.
SLEEP
DVDD
AGND
ICOMP2
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
QD4
QD5
QD6
QD7
QD8
QD9
QD10
QD11 (MSB)
CLK
DGND
AGND
QCOMP2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CommLink™ is a trademark of Intersil Corporation.
1 page  
HI5828
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +5.5V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D11-D0, CLK, SLEEP). . . . . . . DVDD + 0.3V
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . .AVDD + 0.3V
Analog Output Current (IOUTA/B, QOUTA/B) . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(LQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All
Typical Values
PARAMETER
TEST CONDITIONS
TA = -40oC TO 85oC
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE
Resolution
12 -
- Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-2.0 ±0.75 +2.0
LSB
Differential Linearity Error, DNL
(Note 8)
-1.0 ±0.5 +1.0
LSB
Offset Error, IOS
Offset Drift Coefficient
(Note 8)
(Note 8)
-0.025 - +0.025 % FSR
- 0.1 - ppm
FSR/oC
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10 ±2 +10 % FSR
With Internal Reference (Notes 2, 8)
-10 ±1 +10 % FSR
Full Scale Gain Drift
With External Reference (Note 8)
- ±50
-
ppm
FSR/oC
With Internal Reference (Note 8)
- ±100
-
ppm
FSR/oC
Full Scale Output Current, IFS
Crosstalk
Gain Matching Between Channels
(DC Measurement)
fCLK = 100MSPS, fOUT = 10MHz
fCLK = 100MSPS, fOUT = 40MHz
As a percentage of Full Scale Range
In dB Full Scale Range
2 - 20 mA
- 85
-
dB
- 64
-
dB
-5 - +5 % FSR
-0.445 - +0.420 dB FSR
Output Voltage Compliance Range (Note 3, 8)
-0.3 - 1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
Output Settling Time, (tSETT)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
(Note 3)
±0.05% (±2 LSB) (Note 8)
RL = 25Ω (Note 8)
Full Scale Step
125 -
- MHz
- 35
-
ns
-5
- pV•s
- 2.5
-
ns
Output Fall Time
Full Scale Step
- 2.5
-
ns
Output Capacitance
- 10
-
pF
Output Noise
IOUTFS = 20mA
- 50
- pA/√Hz
IOUTFS = 2mA
- 30
- pA/√Hz
5
5 Page 
Timing Diagrams
HI5828
CLK
50%
D11-D0
IOUT
1/2 LSB ERROR BAND
tSETT
tPD
FIGURE 2. OUTPUT SETTLING TIME DIAGRAM
V GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
WIDTH (W)
t (ps)
FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
CLK
D11-D0
IOUT
tPW1
tPW2
tSU tSU tSU
tHLD
tHLD
tHLD
50%
tPD tSETT
tPD tSETT
tPD tSETT
FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HI5828.PDF ] | |
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