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PDF HI5812 Data sheet ( Hoja de datos )
| Número de pieza | HI5812 | |
| Descripción | Sampling A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Semiconductor
HI5812
August 1997
CMOS 20 Microsecond, 12-Bit, Sampling A/D
Converter with Internal Track and Hold
Features
Description
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µs
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .50 KSPS
• Built-In Track and Hold
• Guaranteed No Missing Codes Over Temperature
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Maximum Power Consumption. . . . . . . . . . . . . . .25mW
• Internal or External Clock
The HI5812 is a fast, low power, 12-bit, successive
approximation analog-to-digital converter. It can operate from
a single 3V to 6V supply and typically draws just 1.9mA when
operating at 5V. The HI5812 features a built-in track and hold.
The conversion time is as low as 15µs with a 5V supply.
The twelve data outputs feature full high speed CMOS three-
state bus driver capability, and are latched and held through a
full conversion cycle. The output is user selectable: (i.e.) 12-
bit, 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag, and
conversion-start inputs complete the digital interface.
Applications
• Remote Low Power Data Acquisition Systems
• Digital Audio
• DSP Modems
• General Purpose DSP Front End
• µP Controlled Measurement System
• Professional Audio Positioner/Fader
An internal clock is provided and is available as an output.
The clock may also be over-driven by an external source.
Ordering Information
PART
NUMBER
HI5812JIP
HI5812KIP
HI5812JIB
HI5812KIB
HI5812JIJ
HI5812KIJ
INL (LSB)
(MAX OVER
TEMP.)
TEMP.
RANGE
(oC)
PACKAGE
PKG.
NO.
±1.5 -40 to 85 24 Ld PDIP E24.3
±1.0 -40 to 85 24 Ld PDIP E24.3
±1.5 -40 to 85 24 Ld SOIC M24.3
±1.0 -40 to 85 24 Ld SOIC M24.3
±1.5 -40 to 85 24 Ld CERDIP F24.3
±1.0 -40 to 85 24 Ld CERDIP F24.3
Pinout
HI5812
(PDIP, CERDIP, SOIC)
TOP VIEW
DRDY 1
(LSB) D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
VSS 12
24 VDD
23 OEL
22 CLK
21 STRT
20 VREF-
19 VREF+
18 VIN
17 VAA+
16 VAA-
15 OEM
14 D11 (MSB)
13 D10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
6-1789
File Number 3214.4
1 page  
Timing Diagrams
CLK
(EXTERNAL
OR INTERNAL)
1
STRT
DRDY
23
tD1DRDY
tD2DRDY
HI5812
4
5 - 14
15
tLOW
12
tHIGH
3
D0 - D11
VIN
OEL = OEM = VSS
DATA N - 1
TRACK N
HOLD N
FIGURE 1. CONTINUOUS CONVERSION MODE
DATA N
TRACK N + 1
CLK
(EXTERNAL)
STRT
DRDY
VIN
15 1 2 2 2 3 4 5
tRSTRT
tSUSTRT
tWSTRT
tD3DRDY
HOLD
TRACK
FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK
HOLD
6-1793
5 Page 
HI5812
The input will continue to track until the end of period 3, the
same as when free running.
Figure 2 illustrates the same operation as above but with an
external clock. If STRT is removed (at least tRSTRT) before
clock period 2, a low signal applied to STRT will drop the
DRDY flag as before, and with the first positive-going clock
edge that meets the (tSUSTRT) setup time, the converter will
continue with clock period 3.
Clock
The HI5812 can operate either from its internal clock or from
one externally supplied. The CLK pin functions either as the
clock output or input. All converter functions are synchro-
nized with the rising edge of the clock signal.
Figure 21 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
stray wiring capacitance should be kept to a minimum.
The internal clock will shut down if the A/D is not restarted
after a conversion. The clock could also be shut down with
an open collector driver applied to the CLK pin. This should
only be done during the sample portion (the first three clock
periods) of a conversion cycle, and might be useful for using
the device as a digital sample and hold.
If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again, only during the
sample portion of a conversion cycle. At other times, it must
be above the minium frequency shown in the specifications.
In the above two cases, a further restriction applies in that
the clock should not be shut off during the third sample
period for more than 1ms. This might cause an internal
charge-pump voltage to decay.
If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 15) of the A/D, the
output might be invalid due to balancing capacitor droop.
An external clock must also meet the minimum tLOW and
tHIGH times shown in the specifications. A violation may
cause an internal miscount and invalidate the results.
Except for VAA+, which is a substrate connection to VDD, all
pins have protection diodes connected to VDD and VSS.
Input transients above VDD or below VSS will get steered to
the digital supplies.
The VAA+ and VAA- terminals supply the charge-balancing
comparator only. Because the comparator is autobalanced
between conversions, it has good low-frequency supply
rejection. It does not reject well at high frequencies however;
VAA- should be returned to a clean analog ground and VAA+
should be RC decoupled from the digital supply as shown in
Figure 22.
There is approximately 50Ω of substrate impedance
between VDD and VAA+. This can be used, for example, as
part of a low-pass RC filter to attenuate switching supply
noise. A 10µF capacitor from VAA+ to ground would
attenuate 30kHz noise by approximately 40dB. Note that
back-to-back diodes should be placed from VDD to VAA+ to
handle supply to capacitor turn-on or turn-off current spikes.
Dynamic Performance
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the A/D. A low distor-
tion sine wave is applied to the input of the A/D converter.
The input is sampled by the A/D and its output stored in
RAM. The data is than transformed into the frequency
domain with a 4096 point FFT and analyzed to evaluate the
converters dynamic performance such as SNR and THD.
See typical performance characteristics.
Signal-To-Noise Ratio
The signal to noise ratio (SNR) is the measured RMS signal
to RMS sum of noise at a specified input and sampling
frequency. The noise is the RMS sum of all except the
fundamental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with no
differential or integral linearity error is: SNR = (6.02N + 1.76)
dB. For an ideal 12-bit converter the SNR is 74dB.
Differential and integral linearity errors will degrade SNR.
Sinewave Signal Power
SNR = 10 Log
Total Noise Power
OPTIONAL
EXTERNAL
CLOCK
CLK
INTERNAL
ENABLE
CLOCK
100kΩ
18pF
Signal-To-Noise + Distortion Ratio
SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following:
Sinewave Signal Power
SINAD = 10 Log
Noise + Harmonic Power (2nd - 6th)
FIGURE 21. INTERNAL CLOCK CIRCUITRY
Power Supplies and Grounding
VDD and VSS are the digital supply pins: they power all
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the VDD and VSS
lines, VSS should have a low impedance path to digital
ground and VDD should be well bypassed.
Effective Number of Bits
The effective number of bits (ENOB) is derived from the
SINAD data;
SINAD - 1.76
ENOB =
6.02
6-1799
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HI5812.PDF ] | |
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