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PDF HI5804 Data sheet ( Hoja de datos )

Número de pieza HI5804
Descripción 5 MSPS A/D Converter
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! HI5804 Hoja de datos, Descripción, Manual

Semiconductor
October 1998
NOT RECOMMENSDeEeDHIF5O80R5NEW DESIGNS
HI5804
12-Bit, 5 MSPS A/D Converter
Features
Description
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MSPS
• Low Power
• Internal Sample and Hold
The HI5804 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Harris’ HBC10 BiCMOS process. It is
designed for high speed, high resolution applications where
wide bandwidth and low power consumption are essential.
• Fully Differential Architecture
The HI5804 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
• Full Power Input Bandwidth . . . . . . . . . . . . . . . 100MHz
[ /Title (HI5804)
/SLuobwjeDcits(t1or2t-ioBnit, 5 MSPS A/D Converter)
sample-and-hold (S/H). The HI5804 has excellent dynamic
performance while consuming 300mW power at 5 MSPS.
/AInuttehronral(R) eference
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
/KTeTyLw/CoMrdOsS(CHoamrrpiastiSbelemDiicgoitnaldIu/Octor, A/D, Analog to Daipgp-lications. Data output latches are provided which present
itaDligCitoanl vOeurttpeur,tsN. a. .rr.o. w. . .B.a. n. d. ., .C. o. .m. .m. u. .n.ic. a. .ti3oVntso, 5HVighvalid data to the output bus with a latency of 3 clock cycles.
Speed Converters, High Resolution Converters, BaseTsthae-digital outputs have a separate supply pin which can be
tAiopnp, lCicealltuiolanr)s
powered from a 3.0V to 5.0V supply.
/CHreigahtoSrp(e)ed Data Acquisition Systems
/DOCINFO pdfmark
• Digital IF Communication Systems
[/DPoacguemMeontdaen/dUFsielmOSuctlainnneesrs
/DMOeCdiVcaIlEImWagpindgfmark
Ordering Information
PART
SAMPLE
TEMP.
PKG.
NUMBER
RATE RANGE (oC) PACKAGE NO.
HI5804KCB 5 MSPS
0 to 70 28 Ld SOIC M28.3
• Radar Signal Analysis
HI5804EVAL
25 Evaluation Board
• Vibration/Waveform Spectrum Analysis
• Digital Servo Loop Control
• Reference Literature
- AN9214 Using Harris High Speed Converters
- AN9647 Using the HI5804 Evaluation Board
Pinout
CLK 1
DVCC1 2
DGND1 3
DVCC1 4
DGND1 5
AVCC 6
AGND 7
VIN+ 8
VIN- 9
VDC 10
VROUT 11
VRIN 12
AGND 13
AVCC 14
HI5804
(SOIC)
TOP VIEW
28 D0
27 D1
26 D2
25 D3
24 D4
23 D5
22 DVCC2
21 DGND2
20 D6
19 D7
18 D8
17 D9
16 D10
15 D11
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 4026.5

1 page




HI5804 pdf
Timing Waveforms
ANALOG
INPUT
HI5804
CLOCK
INPUT
SN - 1 HN - 1
SN
HN SN + 1 HN + 1 SN + 2 HN + 2 SN + 3 HN + 3 SN + 4 HN + 4 SN+5 HN + 5 SN + 6 HN + 6
INPUT
S/H
1ST
STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 2
B1, N + 3
B1, N + 4
B1, N + 5
2ND
STAGE
3RD
STAGE
4TH
STAGE
B2, N - 2
B2, N - 1
B2, N
B2, N + 1
B2, N + 2
B2, N + 3
B2, N + 4
B3, N - 2
B3, N - 1
B3, N
B3, N + 1
B3, N + 2
B3, N + 3
B3, N + 4
B4, N - 3
B4, N - 2
B4, N - 1
B4, N
B4, N + 1
B4, N + 2
B4, N + 3
DATA
OUTPUT
DN - 3
DN - 2
DN - 1
DN
NOTES:
tLAT
4. SN: N-th sampling period.
5. HN: N-th holding period.
6. BM, N: M-th stage digital output corresponding to N-th sampled input.DN:
Final data output corresponding to N-th sampled input.
DN + 1
FIGURE 1. HI5804 INTERNAL CIRCUIT TIMING
DN + 2
DN + 3
ANALOG
INPUT
CLOCK
INPUT
tAP
tAJ
1.5V
1.5V
tOD
tH
DATA
OUTPUT
DATA N-1
2.0V
0.8V
DATA N
FIGURE 2. INPUT-TO-OUTPUT TIMING
5

5 Page





HI5804 arduino
HI5804
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0926 0.1043 2.35
2.65
-
A1
0.0040 0.0118 0.10
0.30
-
B
0.013 0.0200 0.33
0.51
9
C
0.0091 0.0125 0.23
0.32
-
D 0.6969 0.7125 17.70 18.10
3
E
0.2914 0.2992 7.40
7.60
4
e 0.05 BSC
1.27 BSC
-
H 0.394 0.419 10.00 10.65
-
h 0.01 0.029 0.25 0.75 5
L
0.016 0.050 0.40
1.27
6
N 28
28 7
α
0o 8o 0o 8o
-
Rev. 0 12/93
11

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