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PDF HI7188 Data sheet ( Hoja de datos )
| Número de pieza | HI7188 | |
| Descripción | Sigma-Delta A/D Sub-System | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HI7188
August 1997
8-Channel, 16-Bit, High Precision,
Sigma-Delta A/D Sub-System
Features
Description
• Fully Differential 8-Channel Multiplexer and Reference
• Automatic Channel Switching with Zero Latency
• 240 Conversions Per Second Per Channel
• 16-Bit Resolution with No Missing Codes
• 0.0015% Integral Non-Linearity
• Fully Software Configurable
- -120dB Rejection of 60/50Hz Line Noise
- Channel Conversion Order and Number of Active
Channels
- True Bipolar or Unipolar Input Range Per Channel
- PGIA Gain Per Channel
- 2-Wire or 3-Wire Interface
• Chopper Stabilized PGIA with Gains of 1 to 8
• Serial Data I/O Interface, SPI Compatible
• 3 Point System Calibration
• Low Power Dissipation of 30mW (Typ)
Applications
• Multi-Channel Industrial Process Controls
• Weight Scales
• Medical Patient Monitoring
• Laboratory Instrumentation
• Gas Monitoring System
• Reference Literature
- AN9504 “A Brief Introduction to Sigma Delta
Conversion”
- TB329 “Intersil Sigma-Delta Calibration Tech-
niques”
- AN9518 “Using the HI7188 Evaluation Kit”
- AN9610 “Interfacing the HI7188 to a Microcontroller”
- AN9538 “Using the HI7188 Serial Interface”
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
The HI7188 is an easy-to-use 8-Channel sigma-delta pro-
grammable A/D subsystem ideal for low frequency physical
and electrical measurements in scientific, medical, and
industrial applications. The subsystem has complete on-chip
capabilities to support moving the intelligence from the sys-
tem controller and towards the sensors. This gives the
designer faster and more flexible configurability without the
traditional drawbacks of low throughput per channel, higher
power or cost per channel. Extreme design complexity and
excessive software overhead is eliminated.
The HI7188 contains a fully differential 8 channel multiplexer,
Programmable Gain Instrumentation Amplifier (PGIA), 4th
order sigma-delta ADC, integrating filter, line noise rejection
filters, calibration and data RAMs, clock oscillator, and a
microsequencer. Communication with the HI7188 is per-
formed via the serial I/O port, and is compatible with most
synchronous transfer formats, including both the Motor-
ola/Intersil 6805/11 series SPI, QSPI and Intel 8051 series
SSR protocols.
The powerful on-board microsequencer provides automatic
conversions on the multiplexed input channels (up to 8) by
controlling all channel switching, filtering and calibration. The
microsequencer supports on-the-fly multiplexer reconfigura-
tion, forty to fifty times faster throughput than the competition
and zero step response delay during internal or external
multiplexer channel changes. A simple set of commands
gives the user control over calibration, PGIA gain, and bipo-
lar/unipolar modes on a per channel basis. Number of chan-
nels to convert, data coding, line noise rejection, etc. is
programmed at the chip level. The calibration RAMs allow
the user to read and write system calibration data while the
data RAMs provide a read support of the conversion results
for each channel.
This design is effectively eight 16-bit (for 96dB noise-free
dynamic range) Sigma-Delta A/D converters combined with
a microsequencer and an eight-channel multiplexer in a sin-
gle package. The HI7188 provides 120dB line-noise rejec-
tion at 240 samples/second/channel (in 60Hz line-rejection
mode) and 200 samples/second/channel (in 50Hz line-rejec-
tion mode) base output data rates. By reusing multiplexer
channels for the same input, throughput can increase by
integer increments of the base output data rate up to
1920Hz.
HI7188IP
-40 to 85 40 Ld PDIP E40.6
HI7188IN
-40 to 85 44 Ld MQFP Q44.10x10
HI7188EVAL
25 Evaluation Kit
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
7-1847
File Number 4016.4
1 page  
HI7188
Pin Descriptions
40 LEAD
PDIP
1
2
3
4
5
6
7
8, 31
9, 30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
38
39
40
44 LEAD
MQFP
41
42
43
44
1
2
3, 30
4, 29, 39
5, 6, 27, 28
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
31
32
33
34
35
36
37
38
40
PIN NAME
PIN DESCRIPTION
MODE Mode input. Used to select between Synchronous Self Clocking (MODE = 1) or Synchronous Ex-
ternal Clocking (MODE = 0) for the Serial Port.
SCLK
Serial interface clock. Synchronizes serial data transfers. Data is input on the rising edge and out-
put on the falling edge.
SDO
Serial Data Out. Serial data is read from this line when using a 3-wire serial protocol such as the
Motorola Serial Peripheral Interface.
SDIO
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel
Standard Serial Interface using a 2-wire serial protocol.
OSC1
Oscillator clock input for the device. A crystal connected between OSC1 and OSC2 will provide a
clock to the device, or an external oscillator can drive OSC1. The oscillator frequency should be
3.6864MHz to maintain Line Noise Rejection.
OSC2
DVDD
DGND
Used to connect a crystal source between OSC1 and OSC2. Leave open otherwise.
Positive Digital supply (+5V).
Digital supply ground.
AVSS
VINL1
VINH1
VINL2
VINH2
VINL3
VINH3
VINL4
VINH4
VINL5
VINH5
VINL6
VINH6
VINL7
VINH7
VINL8
VINH8
VCM
VRLO
VRHI
AVDD
RST
Negative analog power supply (-5V).
Analog input low for Channel 1.
Analog input high for Channel 1.
Analog input low for Channel 2.
Analog input high for Channel 2.
Analog input low for Channel 3.
Analog input high for Channel 3.
Analog input low for Channel 4.
Analog input high for Channel 4.
Analog input low for Channel 5.
Analog input high for Channel 5.
Analog input low for Channel 6.
Analog input high for Channel 6.
Analog input low for Channel 7.
Analog input high for Channel 7.
Analog input low for Channel 8.
Analog input high for Channel 8.
Common mode voltage. Must be tied to the mid point of AVDD and AVSS.
External reference input. Should be negative referenced to VRHI.
External reference input. Should be positive referenced to VRLO.
Positive analog power supply (+5V).
Active low Reset pin. Used to initialize modulator, filter, RAMs, registers and state machines.
CA Calibration active output. Indicates that at least one active channel is in a calibration mode.
MXC Multiplexer control output. Indicates that the conversion for the active channel is complete.
A0
A1
A2
EOS
Logical channel count output (LSB).
Logical channel count output.
Logical channel count output (MSB).
End of scan output. Signals the end of a channel scan (all active channels have been converted)
and data is available to be read. Remains low until data RAM is read.
RSTI/O I/O reset (active low) input. Resets serial interface state machine only.
CS Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and
SDIO pins are three-state.
7-1851
5 Page 
HI7188
(RESET) INITIAL SYSTEM START
PROGRAM THE SYSTEM LEVEL
INFORMATION IN THE
CONTROL REGISTER (CR)
APPLY A ZERO SCALE INPUT
TO EACH OF THE CHANNELS
PROGRAM THE CHANNEL LEVEL
INFORMATION IN THE
CHANNEL CONFIGURATION
REGISTERS (CCR)
AND PLACE EACH CHANNEL
IN OFFSET CALIBRATION MODE
YES
CA OUTPUT
INTERRUPT ACTIVE?
NO
APPLY A POSITIVE FULL SCALE INPUT
TO EACH CHANNEL
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
POSITIVE FULL SCALE
CALIBRATION MODE
YES
CA OUTPUT
INTERRUPT ACTIVE?
NO
APPLY A NEGATIVE FULL SCALE
INPUT TO EACH CHANNEL
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
NEGATIVE FULL SCALE
CALIBRATION MODE
YES
CA OUTPUT
INTERRUPT ACTIVE?
NO
CONNECT DESIRED ANALOG INPUT,
READ DATA RAM VIA
SERIAL INTERFACE
NO EOS OUTPUT
INTERRUPT ACTIVE?
YES
NO
RECALIBRATION REQUIRED?
YES
FIGURE 7. SYSTEM USAGE FLOWCHART
PHYSICAL
CHANNELS
REFERENCE INPUTS
VIN1H
VIN2H
VIN3H
VIN4H
VIN5H
VIN6H
VIN7H
VIN8H
VCM
VRHI VRLO
VIN1L
VIN2L
VIN3L
VIN4L
VIN5L
VIN6L
VIN7L
VIN8L
PGIA
4TH
ORDER
∑−∆
MODULATOR
DIGITAL
SECTION
CONVERSION
CONTROL
FIGURE 8. ANALOG BLOCK DIAGRAM
Analog Inputs
The analog inputs on the HI7188 are fully differential inputs
with programmable gain capabilities. The inputs accept both
unipolar and bipolar input signals and gains of 1, 2, 4 or 8.
The gain for any given physical channel is independent of
the gain of other physical channels. The gain is programmed
via the Channel Configuration Register (CCR).
The input impedance of the HI7188 is dependent upon the
modulator input sampling capacitors which varies with the
selected PGIA gain. Table 2 shows the sampling capacitors
and input impedances for the different gain settings of the
HI7188. Note that this table is valid only for a 3.6864MHz
master clock. If the input clock frequency is changed then
the input impedance will change accordingly. The equation
used to calculate the input impedance is
ZIN = 1/(CS x FS)
Where CS is the internal sampling capacitance and FS is the
modulator sampling rate set by the master clock divided by
six (FS = 3.6864MHz/6 = 614.4kHz).
TABLE 2. EFFECTIVE INPUT IMPEDANCE vs GAIN
GAIN
SAMPLING
RATE
(kHz)
SAMPLING
CAPACITOR
(pF)
INPUT
IMPEDANCE
(kΩ)
1 614.4 4
407
2 614.4 8
203
4
614.4
16
102
8
614.4
32
51
7-1857
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet HI7188.PDF ] | |
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