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PDF HI2302 Data sheet ( Hoja de datos )

Número de pieza HI2302
Descripción Video A/D Converter
Fabricantes Intersil Corporation　
Logotipo Intersil Corporation Logotipo



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No Preview Available ! HI2302 Hoja de datos, Descripción, Manual

®
Pb-Free
DanadtaRSohHeSeCt ompliant
October 25, 2005
HI2302
FN4105.2
8-Bit, 50MSPS, Video A/D Converter with
Clamp Function
The HI2302 is an 8-bit CMOS A/D Converter for video with
synchronizing clamp function. The adoption of two-step
parallel method achieves low power consumption and a
maximum conversion rate of 50MSPS. For pin compatible
lower sample rate converters refer to HI1179 (35MSPS) or
HI1176 (20MSPS) data sheets.
Ordering Information
PART
NUMBER
HI2302JCQ
TEMP.
RANGE (oC)
PACKAGE
-40 to 85 32 Ld MQFP
PKG. NO.
Q32.7x7-S
Applications
• Video Digitizing
• Wireless Receivers
• LCD Projectors/Panels
• Cable Modems
• RGB Graphics Processing
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• Camcorders
• Instrumentation
Features
• Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit ±0.5 LSB (DNL)
• Maximum Sampling Frequency . . . . . . . . . . . . . 50 MSPS
• Low Power Consumption . . . . . . . . . . . . . . . . . . . .125mW
(Reference Current Excluded)
• Built-In Input Clamp Function (DC Restore)
• Clamp ON/OFF Function
• Internal Voltage Reference
• Input CMOS/TTL Compatible
• Three-State TTL Compatible Output
• Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . +5V Single
or +5V/3.3V Dual
• Direct Replacement for Sony CXD2302Q
Pinout
HI2302 (MQFP)
TOP VIEW
D0
132
31
30 29 28 27 26 25
24
VRB
D1 2
23 AVSS
D2 3
22 AVSS
D3 4
21 VIN
D4 5
20 AVDD
D5 6
19 AVDD
D6 7
18 VRT
D7
8 17
9 10 11 12 13 14 15 16
VRTS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1997, 2000, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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HI2302 pdf
Timing Diagrams
CLOCK 1.3V
tPW1 tPW0
ANALOG INPUT
DATA OUTPUT
N
N-3
HI2302
N+1
N-2
N+2
N-1
N+3
N
N+4
N+1
= ANALOG SIGNAL SAMPLING POINT
FIGURE 1A. TIMING CHART
CLOCK
tr
4ns
1.3V
tf
4ns
90%
10%
0.7 DVDD
DATA OUTPUT
0.3 DVDD
tPLH,
tPHL
FIGURE 1B. TIMING CHART
3V
0V
tr = 4.5ns
OE INPUT
1.3V
tPLZ
tf = 4.5ns
90%
10%
tPZL
OUTPUT 1
OUTPUT 2
tPHZ
10%
90%
1.3V
tPZH
1.3V
3V
0V
VOH
VOL (≠DVSS)
VOH (≠DVDD)
VOL
FIGURE 1C. TIMING CHART
5

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HI2302 arduino
HI2302
Application Circuits
CLOCK IN
CLAMP PULSE IN
VIDEO IN
ACO4
0.01µ
+5V (ANALOG)
10µ 33Ω
+
10P
0.1µ
OPEN
16 15 14 13 12 11 10 9
17 8
18 7
19 6
20 5
21 4
22 3
23 2
+5V (ANALOG)
0.01µ
VREF
20K
24 1
25 26 27 28 29 30 31 32
0.01µ
GND (ANALOG)
GND (DIGITAL)
+5V (DIGITAL)
0.1µ
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 7. SINGLE +5V POWER SUPPLY WHEN CLAMP IS USED (SELF-BIAS USED)
CLOCK IN
ACO4
0.01µ
+5V (ANALOG)
VIDEO IN
10µ 33Ω
+
10p
0.1µ
OPEN
16 15 14 13 12 11 10 9
17 8
18 7
19 6
20 5
21 4
22 3
23 2
+5V (DIGITAL)
0.1µ
SUBTRACTER
•
COMPARATOR
•
ETC.
CLAMP LEVEL
SETTING DATA
0.01µ
24 1
25 26 27 28 29 30 31 32
GND (DIGITAL)
DAC
•
PWM
•
ETC.
GND (ANALOG)
INFORMATION OTHER
THAN THAT FOR CLAMP
INTERVAL IS AT HIGH
IMPEDANCE
NOTES:
5. The relationship between the changes in CCP voltage (Pin 27) and in VIN voltage is positive phase.
6. ∆ VIN/ ∆ VCCP = 3.0 (fS = 20 MSPS).
FIGURE 8. SINGLE +5V POWER SUPPLY DIGITAL CLAMP (SELF-BIAS USED)
11

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