|
|
PDF HI2325 Data sheet ( Hoja de datos )
| Número de pieza | HI2325 | |
| Descripción | 40MSPS A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HI2325 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
TM
Data Sheet
HI2325
March 2000 File Number 4823.1
3.3V Dual 8-Bit, 40MSPS A/D Converter
with Internal Reference and Digital Clamp
The HI2325 is a monolithic, dual 8-bit, 40MSPS analog-to-
digital converter fabricated in an advanced CMOS process.
It is designed for high speed applications where integration,
bandwidth and accuracy are essential. The HI2325 features
a 2-stage parallel architecture. Only one external clock is
necessary to drive both converters and an internal voltage
reference is provided allowing the system designer to realize
an increased level of system integration resulting in
decreased cost and power dissipation.
The HI2325 has excellent dynamic performance while
consuming less than 100mW power at 40MSPS. The A/D
only requires a single +3.3V power supply and encode clock.
Data output latches are provided which present valid data to
the output bus with a latency of 2 clock cycles.
Ordering Information
PART
NUMBER
HI2325IN
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
-20 to 85 48 Ld MQFP/PQFP Q48.7x7-S
www.DataSheet4U.com
Pinout
48 LEAD LQFP
TOP VIEW
A3
A4
A5
A6
A7
DVDD
DVDD
B0
B1
B2
B3
B4
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
AVSS
AIO
AIN
AVDD
ART
ARTS
BRTS
BRT
AVDD
BIN
BIO
AVSS
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS
• 6.5 Bits at fIN = 1MHz
• Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW
• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
• Internal Digital Clamp
• Internal Voltage Reference
• Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.3V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs . . . . . . . . . . . . . . . 3.3V
• Offset Binary or 2’s Complement Output Format
• Dual 8-Bit A/D Converters on a Monolithic Chip
Applications
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging and Instrumentation
• Portable Communications
• Power Metering
• Hand-Held Data Collection Instruments
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
HI2325
Electrical Specifications
AVDD = DVDD
CL = 10pF; TA
=
=
2+53o.3CV; ;UVnIlNes=s1O.5th0eVr;wfSise=
40MSPS
Specified
at 50% Duty Cycle;
(Continued)
PARAMETER
TEST CONDITIONS
MIN
Analog Input Bias Current, IBA or IBB
VINA/VINB = ART/BRT, ARB/BRB, DC
(Notes 2, 3)
-
Full Power Input Bandwidth, FPBW
REFERENCE VOLTAGE INPUT
fS = 40MHz, (Note 2)
-
Reference Voltage Input Range
-
Total Reference Resistance, RRIN
Reference Current, IRIN
Self Bias
SAMPLING CLOCK INPUT
VRB
VRT
-
-
-
-
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic High Current, IIH
Input Logic Low Current, IIL
Input Capacitance, CIN
DIGITAL OUTPUTS
CLK
CLK
CLK, VIH = 3.3V
CLK, VIL = 0V
CLK
2.0
-
-
-
-
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Capacitance, COUT
TIMING CHARACTERISTICS
IOH = 100µA; DVDD = 3.3V
IOL = 1.5mA; DVDD = 3.3V
IOH = 100µA; DVDD = 3.0V
IOL = 100µA; DVDD = 3.0V
-
-
-
-
-
Aperture Delay, tAP
Aperture Jitter, tAJ
Data Output Hold, tH
Data Output Delay, tOD
Data Latency, tLAT
Power-Up Initialization
For a Valid Sample (Note 2)
Data Invalid Time (Note 2)
-
-
-
-
2
-
Sample Clock Pulse Width (Low)
(Note 2)
11.25
Sample Clock Pulse Width (High)
(Note 2)
11.25
Sample Clock Duty Cycle Variation
-
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVDD
Digital Supply Voltage, DVDD
Supply Current, IDD
Power Dissipation
(Note 2)
(Note 2)
fS = 40MSPS
3.0
3.0
-
-
Offset Error Sensitivity, ∆VOS
A VDD or DVDD = 3.3V ±5%
Gain Error Sensitivity, ∆FSE
A VDD or DVDD = 3.3V ±5%
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
-
-
TYP
-
-
-
370
5.4
0.54
1.9
-
-
-
-
-
-
-
-
-
-
4
5
10.7
11.7
2
-
12.5
12.5
±5
3.3
3.3
30.3
100
±0.125
±0.15
MAX
-
-
-
-
-
-
-
-
0.8
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
3.6
3.6
-
-
-
-
UNITS
µA
MHz
V
kΩ
mA
V
V
µA
µA
pF
V
V
V
V
pF
ns
psRMS
ns
ns
Cycles
Cycles
ns
ns
%
V
V
mA
mW
LSB
LSB
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HI2325.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HI2325 | 40MSPS A/D Converter | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |