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PDF HI3300 Data sheet ( Hoja de datos )
| Número de pieza | HI3300 | |
| Descripción | 20MSPS A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HI3300 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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TM
Data Sheet
HI3300
March 2000 File Number 4822.1
3V 10-Bit, 20MSPS A/D Converter with
Internal Voltage Reference
The HI3300 is a monolithic, 10-bit analog-to-digital converter
fabricated in an advanced CMOS process. It is designed for
high speed applications where integration, bandwidth and
accuracy are essential. The HI3300 features a 2-step
parallel architecture to allow the system designer to realize
an increased level of system integration resulting in
decreased cost and power dissipation.
The HI3300 has excellent dynamic performance while
consuming less than 40mW power at 20MSPS. The A/D only
requires a single +3.0V power supply.
Ordering Information
PART
NUMBER
HI3300IN
TEMP.
RANGE
(oC)
SAMPLING
RATE
PACKAGE PKG. NO. (MSPS)
-40 to 85 48 Ld LQFP Q48.7x7-S
20
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Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .20MSPS
• Low Power at 20MSPS. . . . . . . . . . . . . . . . . . . . . . .40mW
• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 100MHz
• On-Chip Sample and Hold Amplifiers
• Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.3V
Applications
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging
• Wireless Communications Systems
• Battery Powered Instruments
Pinout
HI3300
48 LEAD LQFP
TOP VIEW
DO
D1
D2
D3
D4
DVSS
DVDD
D5
D6
D7
D8
D9
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
BE
AVDD
AVSS
VRBS
VRB
VRBC
VRMC
VRTC
VRT
VRTS
AVDD
AVSS
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
Timing Diagrams
tPW1
tPW0
HI3300
CLOCK
1.5V
tSD
ANALOG INPUT
N
tDL
DATA OUTPUT
N +1
N -3
N +2
N -2
N +3
N -1
N +4
N
1.5V
NOTE: : Indicates point at which analog data is sampled.
FIGURE 1. TIMING CHART 1
OUTPUT ENABLE (OE)
1.5V
tPEZ
1.5V
tPZE
1.5V
DATA OUTPUT
ACTIVE
HIGH IMPEDANCE
ACTIVE
FIGURE 2. TIMING CHART 2
5
5 Page 
HI3300
Application Circuit 1
When not using self-bias and the internal bias circuits and supplying the reference voltage from an external source.
AVDD
1V 2V
AVDD
2.0V
AVDD
1.0V
SIGNAL INPUT
CALIBRATION
PULSE
AVSS
DVDD
DVSS
36 35 34 33 32 31 30 29 28 27 26 25
AVSS
37 TSTR
38 VIN
39 TS
40 AVDD
41 AVSS
42 CAL
43 AVDD
44 AT
45 AVDD
46 AVSS
47 DVDD
48 DVSS
CE 24
OE 23
CLK 22
AVDD 21
MINV 20
LINV 19
TESTMODE 18
AVDD 17
AVSS 16
RESET 15
TIN 14
TO 13
AVDD
AVSS
CLOCK
PULSE
RESET
PULSE
1 2 3 4 5 6 7 8 9 10 11 12
DVSS
DVDD
: 0.1µF
POWER SUPPLY
DECOUPLERS
DIGITAL OUTPUT
NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any
problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HI3300.PDF ] | |
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