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PDF HI3306 Data sheet ( Hoja de datos )
| Número de pieza | HI3306 | |
| Descripción | Flash A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HI3306
December 1997
6-Bit, 15 MSPS, Flash A/D Converter
Features
Description
• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . .55mW
• Parallel Conversion Technique
• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• Sampling Rate with Single 5V Supply . . . . . . . . 15MHz
• 6-Bit Latched Three-State Output with Overflow Bit
• Linearity (INL, DNL):
- HI3306JIP/15 . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
- HI3306JIP/10 . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
- HI3306JIB/15 . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
- HI3306JIB/10 . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
• Sampling Rate:
- HI3306JIP/15 . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)
- HI3306JIP/10 . . . . . . . . . . . . . . . . . . . . 10MHz (100ns)
- HI3306JIB/15 . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)
- HI3306JIB/10 . . . . . . . . . . . . . . . . . . . . 10MHz (100ns)
Applicationswww.DataSheet4U.com
• Video Digitizing
• Digital Communication Systems
• High Speed Data Acquisition
• Radar Signal Processing
The HI3306 family are CMOS parallel (FLASH) analog-to-
digital converters designed for applications demanding
both low power consumption and high speed digitization.
Digitizing at 15MHz, for example, requires only about
55mW.
The HI3306 family operates over a wide, full scale signal input
voltage range of 1V up to the supply voltage. Power consump-
tion is as low as 15mW, depending upon the clock frequency
selected. The HI3306 offers improved linearity at a lower ref-
erence voltage and high operating speed with a 5V supply.
The overflow bit makes possible the connection of two or
more HI3306s in series to increase the resolution of the
conversion system.
Sixty-four paralleled auto balanced comparators measure
the input voltage with respect to a known reference to pro-
duce the parallel bit outputs in the HI3306. Sixty-three com-
parators are required to quantize all input voltage levels in
this 6-bit converter, and the additional comparator is
required for the overflow bit.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI3306JIP/15
-40 to 85 18 Ld PDIP
HI3306JIP/10
-40 to 85 18 Ld PDIP
HI3306JIB/15
-40 to 85 20 Ld SOIC
PKG. NO.
E18.3
E18.3
M20.3
HI3306JIB/10
-40 to 85 20 Ld SOIC
M20.3
Pinouts
HI3306 (PDIP)
TOP VIEW
(MSB) B6 1
OVERFLOW 2
VSS 3
VZ 4
CE2 5
CE2 6
CLK 7
PHASE 8
VREF+ 9
18 B5
17 B4
16
REF
CENTER
15 B3
14 B2
13 B1 (LSB)
12 VDD
11 VIN
10 VREF-
HI3306 (SOIC)
TOP VIEW
(MSB) B6 1
OVERFLOW 2
VSS 3
NC 4
VZ 5
CE2 6
CE1 7
CLK 8
PHASE 9
VREF+ 10
20 B5
19 B4
18
REF
CENTER
17 B3
16 B2
15 B1 (LSB)
14 VDD
13 NC
12 VIN
11 VREF-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
File Number 4136.2
1 page  
Timing Waveforms
CE1
HI3306
CE2
BITS 1-6
tDIS
DATA
tEN
HIGH
IMPEDANCE
tDIS
DATA
tDIS
HIGH
IMPEDANCE
DATA
OF DATA
HIGH
IMPEDANCE
DATA
SAMPLE ENDS
CLOCK
φ2
φ1
OUTPUT
OLD DATA
FIGURE 2. OUTPUT ENABLE
SAMPLE ENDS
φ2
CLOCK φ 1
φ2
φ1 φ2
tD tD
NEW DATA
OUTPUT
OLD
DATA
OLD
DATA +1
FIGURE 3A.
CLOCK
φ2
SAMPLE ENDS
φ1 φ2
φ1
FIGURE 3B.
φ2
OUTPUT
OLD DATA
tD
INVALID
DATA
NEW
DATA
φ1
NEW
DATA
FIGURE 3C.
FIGURE 3. PULSE MODE
Typical Performance Curves
50
TA = 25oC, VREF+ = VDD
VIN = 0 TO VREF+ SINE WAVE AT fCLK/2
40
30 VDD = 8V
VDD = 7V
VDD = 6V
20 VDD = 5V
DISSIPATION LIMITED
125
fCLK = 3MHz
fCLK = 10MHz
fCLK = 15MHz
100 fCLK = 20MHz
MAXIMUM AMBIENT
75 TEMPERATURE - PLASTIC
fCLK = 1MHz
10
VDD = 3V
0.1 1
10
CLOCK FREQUENCY (MHz)
FIGURE 4. TYPICAL IDD AS A FUNCTION OF VDD
50
VREF+ = VDD
VIN = 0 TO VREF+ SINE WAVE AT fCLK/2
ZENER NOT CONNECTED
25
3456
VDD (V)
7
8
FIGURE 5. TYPICAL MAXIMUM AMBIENT TEMPERATURE AS
A FUNCTION OF SUPPLY VOLTAGE
5
5 Page 
HI3306
verter. The three-state outputs of the two devices (bits 1
through 6) are now connected in parallel to complete the
circuitry.
Doubled Sampling Speed
The phase control and both positive and negative true chip
enables allow the parallel connection of two HI3306s to
double the sampling speed. Figure 18 shows this configu-
ration. One converter samples on the positive phase of the
clock, and the second on the negative. The outputs are
also alternately enabled. Care should be taken to provide a
near square-wave clock it operating at close to the maxi-
mum clock speed for the devices.
8-Bit to 12-Bit Conversion Techniques
To obtain 8-bit to 12-bit resolution and accuracy, use a
feed- forward conversion technique. Two A/D converters
will be needed to convert up to 11 bits; three A/D convert-
ers to convert 12 bits. The high speed of the HI3306 allows
12-bit conversions in the 500ns to 900ns range.
The circuit diagram of a high-speed 12-bit A/D converter is
shown in Figure 19. In the feed-forward conversion method
two sequential conversions are made. Converter A first
does a coarse conversion to 6 bits. The output is applied to
a 6-bit D/A converter whose accuracy level is good to 12
bits. The D/A converter output is then subtracted from the
input voltage, multiplied by 32, and then converted by a
second flash A/D converter, which is connected in a 7-bit
configuration. The answers from the first and second con-
versions are added together with bit 1 of the first conver-
sion overlapping bit 7 of the second conversion.
When using this method, take care that:
• The linearity of the first converter is better than 1/2 LSB.
• An offset bias of 1 LSB (1/64) Is subtracted from the first
conversion since the second converter is unipolar.
• The D/A converter and its reference are accurate to the
total number of bits desired for the final conversion (the A/D
converter need only be accurate to 6 bits).
The first converter can be offset-biased by adding a 20Ω
resistor at the bottom of the ladder and increasing the reference
voltage by 1 LSB. If a 6.4V reference is used in the system, for
example, then the first HI3306 will require a 6.5V reference.
Definitions
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the converter. A low distortion sine
wave is applied to the input, it is sampled, and the output is
stored in RAM. The data is then transformed into the frequency
domain with a 4096 point FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from full scale for all these tests.
Signal-to-Noise (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency
excluding DC.
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76 + VCORR)/6.02,
where: VCORR = 0.5dB.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the measured input
signal.
Operating and Handling Considerations
HANDLING
All inputs and outputs of Intersil CMOS devices have a net-
work for electrostatic protection during handling. Recom-
mended handling practices for CMOS devices are
described in AN6525. “Guide to Better Handling and Oper-
ation of CMOS Integrated Circuits.”
OPERATING
Operating Voltage
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause
VDD - VSS to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection circuit, input sig-
nals should never be greater than VDD nor less than VSS.
Input currents must not exceed 20mA even when the power
supply is off. The Zener (pin 4) is the only terminal allowed
to exceed VDD.
Unused Inputs
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VDD or
VSS, whichever is appropriate.
Output Short Circuits
Shorting of outputs to VDD or VSS may damage CMOS
devices by exceeding the maximum device dissipation.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HI3306.PDF ] | |
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