HI3318 PDF даташит
Спецификация HI3318 изготовлена «Intersil Corporation» и имеет функцию, называемую «Flash A/D Converter». |
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Детали детали
Номер произв | HI3318 |
Описание | Flash A/D Converter |
Производители | Intersil Corporation |
логотип |
12 Pages
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HI3318
August 1997
8-Bit, 15 MSPS, Flash A/D Converter
Features
Description
• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . 150mW
• Parallel Conversion Technique
• Sampling Rate at 5V Supply . . . . . . . . . . . . . . . . 15MHz
• 8-Bit Latched Three-State Output with Overflow Bit
• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB
• Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V
• Linearity (INL):
- HI3318JIP . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5 LSB
- HI3318JIB . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5 LSB
• Sampling Rate:
- HI3318JIP . . . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)
- HI3318JIB . . . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)
• Video Digitizing
• High-Speed A/D Conversion
• Medical Imaging
www.DataSheet4U.com • Radar Signal Processing
• Digital Communications Systems
The HI3318 is a CMOS parallel (FLASH) analog-to-digital
converter designed for applications demanding both low
power consumption and high speed digitization.
The HI3318 operates over a wide full scale input voltage
range of 4V up to 7.5V with maximum power consumption
depending upon the clock frequency selected. When oper-
ated from a 5V supply at a clock frequency of 15MHz, the
typical power consumption of the HI3318 is 150mW.
256 paralleled auto balanced voltage comparators measure
the input voltage with respect to a known reference to pro-
duce the parallel bit outputs in the HI3318. 255 comparators
are required to quantize all input voltage levels in this 8-bit
converter, and the additional comparator is required for the
overflow bit.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI3318JIP
-40 to 85 24 Ld PDIP
HI3318JIB
-40 to 85 24 Ld SOIC
PKG.
NO.
E24.6
M24.3
Pinout
HI3318
(PDIP, SOIC)
TOP VIEW
(LSB) B1 1
B2 2
B3 3
B4 4
B5 5
B6 6
B7 7
(MSB) B8 8
OVERFLOW 9
1/4R 10
(DIG. GND) VSS 11
(DIG. SUP.) VDD 12
24 VAA+ (ANA. SUP.)
23 3/4R
22 VREF+
21 VIN
20 p
19 PHASE
18 CLK
17 VAA- (ANA. GND)
16 VIN
15 VREF -
14 CE1
13 CE2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-1452
File Number 4135.1
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HI3318
Functional Block Diagram
VAA+
24
ANALOG φ2 φ1
SUPPLY
VIN
21
VREF+ 1/2 R
22
R = 2Ω
3/4 REF
23
= 7Ω
R
R
1/2 REF
20
= 30Ω
R
R
1/4 REF
10
= 4Ω
R
VIN R
16
R ≅ 2K
VREF -
15
1/2 R
≅ 50K
CLOCK
18
PHASE
19
VAA-
17
ANALOG
GND
φ1 φ1
CAB
# 256
CAB
# 193
CAB
# 129
φ1 φ2
VDD
φ1
DIGITAL
SUPPLY
12
DQ
LATCH
256
DQ
COUNT
256
DQ
LATCH
256
ENCODER
LOGIC
COUNT ARRAY
193
DQ
THREE-
OUTPUT STATE
REGISTER DRIVERS OVER-
FLOW
DQ
9
CLK
DQ
BIT 8
(MSB)
8
CLK
DQ
BIT 7
7
CLK
LATCH
DQ
LATCH
COUNT
129
DQ
DQ
CLK
DQ
BIT 6
6
BIT 5
5
LATCH
LATCH
CLK
CAB
# 65
DQ
COUNT
65
DQ
LATCH
LATCH
DQ
CLK
DQ
CLK
BIT 4
4
BIT 3
3
CAB
(NOTE 1)
COMPARATOR #1
DQ
LATCH
1
COUNT
1
DQ
LATCH
11
φ1 (AUTO BALANCE)
DQ
CLK
DQ
CLK
BIT 2
2
BIT 1
(LSB)
1
φ2 (SAMPLE UNKNOWN)
CE1
14
CE2
13
DIGITAL
GND
VSS
11
NOTE:
1. Cascaded Auto Balance (CAB).
4-1453
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HI3318
Absolute Maximum Ratings TA = 25oC
DC Supply Voltage Range (VDD or VAA+) . . . . . . . . . . -0.5V to +8V
(Referenced to VSS or VAA- Terminal, Whichever is
More Negative)
Input Voltage Range
CE2 and CE1 . . . . . . . . . . . . . . . . . . . . VAA- -0.5V to VDD + 0.5V
Clock, Phase, VREF -,
VCIlNoc, k3,/4PRhaEsFe,,VVRREEFF+-.,
11//24
...
Ref
Ref
...
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
VAA- -0.5V to VAA+
. VSS- -0.5V to VDD
. VAA- -0.5V to VAA-
+
+
+
0.5V
0.5V
7.5V
Output Voltage Range, . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V
Bits 1-8, Overflow (Outputs Off)
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Clock, Phase, CE1, CE2, VIN, Bits 1-8, Overflow
Recommended VAA+ Operating Range . . . . . . . . . . . . . . . VDD ±1V
Recommended VAA- Operating Range . . . . . . . . . . . . . . . VSS ±1V
Operating Conditions
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Voltage Range
Temperature Range (TA)
(VDD
.....
or
..
VAA+)
.....
.
.
.
.
.
.
4V
...
(Min) to 7.5V (Max)
. . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications At 25oC, VAA+ = VDD = 5V, VREF+ = 6.4V, VREF - = VAA- = VSS, CLK = 15MHz,
All Reference Points Adjusted, Unless Otherwise Specified
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error
Differential Linearity Error
Offset Error, Unadjusted
Gain Error, Unadjusted
DYNAMIC CHARACTERISTICS
Maximum Input Bandwidth
Maximum Conversion Speed
Signal to Noise Ratio, SNR
= R-R----M-M----S-S-----S-N----i-o-g---i-n-s--a-e---l
TEST CONDITIONS
VIN = VREF- + 1/2 LSB
VIN = VREF+ - 1/2 LSB
(Note 1) HI3318
CLK = Square Wave
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
MIN
TYP
MAX
UNITS
8 - - Bits
-
-
± 1.5
LSB
-
-
+1, -0.8
LSB
-0.5 4.5 6.4 LSB
-1.5 0
1.5 LSB
2.5 5.0
15 17
- 47
- 43
- MHz
- MSPS
- dB
- dB
Signal to Noise Ratio, SINAD
= R-----M-----S----N-R----oM----i-S-s---e---S---+--i-g--D--n---i-as---t-l-o---r--t--i-o---n--
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
- 45 -
- 35 -
dB
dB
Total Harmonic Distortion, THD
Effective Number of Bits, ENOB
Differential Gain Error
Differential Phase Error
ANALOG INPUTS
Full Scale Range, VIN and (VREF+) - (VREF-)
Input Capacitance, VIN
Input Current, VIN, (See Text)
REFERENCE INPUTS
Ladder Impedance
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
fS = 15MHz, fIN = 100kHz
fS = 15MHz, fIN = 4MHz
Unadjusted
Unadjusted
Notes 2, 4
VIN = 5.0V, VREF+ = 5.0V
- -46 -
- -36 -
- 7.2 -
- 5.5 -
-2-
-1-
4-7
- 30 -
- - 3.5
270 500 800
dBc
dBc
Bits
Bits
%
%
V
pF
mA
Ω
4-1454
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